Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/evergreen_textured

Lines Matching refs:accel_state
66     struct radeon_accel_state *accel_state = info->accel_state;
183 			   accel_state->xv_vs_offset, accel_state->xv_ps_offset,
195     radeon_vbo_check(pScrn, &accel_state->vbo, 16);
196     radeon_vbo_check(pScrn, &accel_state->cbuf, 512);
201     evergreen_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
202     evergreen_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
203     evergreen_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
219     vs_conf.shader_addr         = accel_state->vs_mc_addr;
220     vs_conf.shader_size         = accel_state->vs_size;
223     vs_conf.bo                  = accel_state->shaders_bo;
226     ps_conf.shader_addr         = accel_state->ps_mc_addr;
227     ps_conf.shader_size         = accel_state->ps_size;
232     ps_conf.bo                  = accel_state->shaders_bo;
239 	accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
243 	tex_res.w                   = accel_state->src_obj[0].width;
244 	tex_res.h                   = accel_state->src_obj[0].height;
245 	tex_res.pitch               = accel_state->src_obj[0].pitch;
248 	tex_res.base                = accel_state->src_obj[0].offset;
249 	tex_res.mip_base            = accel_state->src_obj[0].offset;
250 	tex_res.size                = accel_state->src_size[0];
251 	tex_res.bo                  = accel_state->src_obj[0].bo;
252 	tex_res.mip_bo              = accel_state->src_obj[0].bo;
265 	if (accel_state->src_obj[0].tiling_flags == 0)
267 	evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
286 	tex_res.w                   = accel_state->src_obj[0].width >> 1;
287 	tex_res.h                   = accel_state->src_obj[0].height >> 1;
288 	tex_res.pitch               = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
295 	tex_res.base                = accel_state->src_obj[0].offset + pPriv->planev_offset;
296 	tex_res.mip_base            = accel_state->src_obj[0].offset + pPriv->planev_offset;
298 	if (accel_state->src_obj[0].tiling_flags == 0)
300 	evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
309 	tex_res.w                   = accel_state->src_obj[0].width >> 1;
310 	tex_res.h                   = accel_state->src_obj[0].height >> 1;
311 	tex_res.pitch               = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
318 	tex_res.base                = accel_state->src_obj[0].offset + pPriv->planeu_offset;
319 	tex_res.mip_base            = accel_state->src_obj[0].offset + pPriv->planeu_offset;
321 	if (accel_state->src_obj[0].tiling_flags == 0)
323 	evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
332 	accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
336 	tex_res.w                   = accel_state->src_obj[0].width;
337 	tex_res.h                   = accel_state->src_obj[0].height;
338 	tex_res.pitch               = accel_state->src_obj[0].pitch >> 1;
341 	tex_res.base                = accel_state->src_obj[0].offset;
342 	tex_res.mip_base            = accel_state->src_obj[0].offset;
343 	tex_res.size                = accel_state->src_size[0];
344 	tex_res.bo                  = accel_state->src_obj[0].bo;
345 	tex_res.mip_bo              = accel_state->src_obj[0].bo;
361 	if (accel_state->src_obj[0].tiling_flags == 0)
363 	evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
382     cb_conf.w = accel_state->dst_obj.pitch;
383     cb_conf.h = accel_state->dst_obj.height;
384     cb_conf.base = accel_state->dst_obj.offset;
385     cb_conf.bo = accel_state->dst_obj.bo;
386     cb_conf.surface = accel_state->dst_obj.surface;
388     switch (accel_state->dst_obj.bpp) {
416     if (accel_state->dst_obj.tiling_flags == 0) {
420     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
427     ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
428     ps_const_conf.bo = accel_state->cbuf.vb_bo;
429     ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset;
447     radeon_vbo_commit(pScrn, &accel_state->cbuf);
453     vs_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
454     vs_const_conf.bo = accel_state->cbuf.vb_bo;
455     vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset;
463     radeon_vbo_commit(pScrn, &accel_state->cbuf);
504 	vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
521 	radeon_vbo_commit(pScrn, &accel_state->vbo);