Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/legacy

Lines Matching refs:ModeReg
661     info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
810 	     /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the
1032 	     /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the
1802     RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
1804     RADEONInitCommonRegisters(info->ModeReg, info);
1806     RADEONInitSurfaceCntl(crtc, info->ModeReg);
1811 	RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode);
1812 	RADEONInitCrtcBase(crtc, info->ModeReg, x, y);
1816 	    RADEONInitPLLRegisters(crtc, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
1818 	    info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div;
1819 	    info->ModeReg->ppll_div_3   = info->SavedReg->ppll_div_3;
1820 	    info->ModeReg->htotal_cntl  = info->SavedReg->htotal_cntl;
1825 	RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode);
1826 	RADEONInitCrtc2Base(crtc, info->ModeReg, x, y);
1830 	    RADEONInitPLL2Registers(crtc, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
1843 		    RADEONAdjustCrtcRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
1844 		    RADEONAdjustPLLRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
1848 		    RADEONAdjustCrtc2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
1849 		    RADEONAdjustPLL2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output);
1857     RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
1859     RADEONRestoreCommonRegisters(pScrn, info->ModeReg);
1864 	RADEONRestoreCrtcRegisters(pScrn, info->ModeReg);
1866 	RADEONRestorePLLRegisters(pScrn, info->ModeReg);
1870 	RADEONRestoreCrtc2Registers(pScrn, info->ModeReg);
1872 	RADEONRestorePLL2Registers(pScrn, info->ModeReg);
1878 	radeon_update_tv_routing(pScrn, info->ModeReg);