Lines Matching refs:restore
62 RADEONSavePtr restore)
71 OUTREG(RADEON_OVR_CLR, restore->ovr_clr);
72 OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
73 OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
74 OUTREG(RADEON_OV0_SCALE_CNTL, restore->ov0_scale_cntl);
75 OUTREG(RADEON_SUBPIC_CNTL, restore->subpic_cntl);
76 OUTREG(RADEON_VIPH_CONTROL, restore->viph_control);
77 OUTREG(RADEON_I2C_CNTL_1, restore->i2c_cntl_1);
78 OUTREG(RADEON_GEN_INT_CNTL, restore->gen_int_cntl);
79 OUTREG(RADEON_CAP0_TRIG_CNTL, restore->cap0_trig_cntl);
80 OUTREG(RADEON_CAP1_TRIG_CNTL, restore->cap1_trig_cntl);
81 OUTREG(RADEON_BUS_CNTL, restore->bus_cntl);
82 OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl);
86 OUTREG(RS400_DISP2_REQ_CNTL1, restore->disp2_req_cntl1);
87 OUTREG(RS400_DISP2_REQ_CNTL2, restore->disp2_req_cntl2);
88 OUTREG(RS400_DMIF_MEM_CNTL1, restore->dmif_mem_cntl1);
89 OUTREG(RS400_DISP1_REQ_CNTL1, restore->disp1_req_cntl1);
109 RADEONSavePtr restore)
115 OUTREG(R300_CRTC_TILE_X0_Y0, restore->crtc_tile_x0_y0);
116 OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
117 OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset);
122 RADEONSavePtr restore)
128 OUTREG(R300_CRTC2_TILE_X0_Y0, restore->crtc2_tile_x0_y0);
129 OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
130 OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset);
136 RADEONSavePtr restore)
143 (unsigned)restore->crtc_offset);
148 OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl |
152 restore->crtc_ext_cntl,
157 OUTREG(RADEON_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
158 OUTREG(RADEON_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
159 OUTREG(RADEON_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
160 OUTREG(RADEON_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
162 RADEONRestoreCrtcBase(pScrn, restore);
164 OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch);
165 OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl);
168 OUTREG(RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
169 OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
170 OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
171 OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
174 OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl);
180 RADEONSavePtr restore)
188 (unsigned)restore->crtc2_offset);
194 restore->crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS |
198 OUTREG(RADEON_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp);
199 OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid);
200 OUTREG(RADEON_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp);
201 OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid);
203 OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp_h2_sync_strt_wid);
204 OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp_v2_sync_strt_wid);
206 RADEONRestoreCrtc2Base(pScrn, restore);
208 OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch);
209 OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl);
211 OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
300 RADEONSavePtr restore)
314 restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
315 restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK);
324 if ((restore->ppll_ref_div == (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
325 (restore->ppll_div_3 == (INPLL(pScrn, RADEON_PPLL_DIV_3) &
359 if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
364 restore->ppll_ref_div,
369 (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
374 restore->ppll_ref_div,
379 restore->ppll_div_3,
383 restore->ppll_div_3,
389 OUTPLL(pScrn, RADEON_HTOTAL_CNTL, restore->htotal_cntl);
400 restore->ppll_ref_div,
401 restore->ppll_div_3,
402 (unsigned)restore->htotal_cntl,
406 restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
407 restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
408 (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
416 /*OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_ecp_cntl);*/
425 RADEONSavePtr restore)
431 restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
432 restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK);
450 restore->p2pll_ref_div,
454 restore->p2pll_div_0,
458 restore->p2pll_div_0,
464 OUTPLL(pScrn, RADEON_HTOTAL2_CNTL, restore->htotal_cntl2);
474 (unsigned)restore->p2pll_ref_div,
475 (unsigned)restore->p2pll_div_0,
476 (unsigned)restore->htotal_cntl2,
480 (unsigned)restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
481 (unsigned)restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
482 (unsigned)((restore->p2pll_div_0 &
491 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl);
557 /* track if the crtc is enabled for text restore */
590 /* track if the crtc is enabled for text restore */
1362 radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore)
1365 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl);
1856 ErrorF("restore memmap\n");
1858 ErrorF("restore common\n");
1863 ErrorF("restore crtc1\n");
1865 ErrorF("restore pll1\n");
1869 ErrorF("restore crtc2\n");
1871 ErrorF("restore pll2\n");