Lines Matching refs:save
499 RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
504 save->ovr_clr = INREG(RADEON_OVR_CLR);
505 save->ovr_wid_left_right = INREG(RADEON_OVR_WID_LEFT_RIGHT);
506 save->ovr_wid_top_bottom = INREG(RADEON_OVR_WID_TOP_BOTTOM);
507 save->ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
508 save->subpic_cntl = INREG(RADEON_SUBPIC_CNTL);
509 save->viph_control = INREG(RADEON_VIPH_CONTROL);
510 save->i2c_cntl_1 = INREG(RADEON_I2C_CNTL_1);
511 save->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL);
512 save->cap0_trig_cntl = INREG(RADEON_CAP0_TRIG_CNTL);
513 save->cap1_trig_cntl = INREG(RADEON_CAP1_TRIG_CNTL);
514 save->bus_cntl = INREG(RADEON_BUS_CNTL);
515 save
516 save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL);
517 save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL);
521 save->disp2_req_cntl1 = INREG(RS400_DISP2_REQ_CNTL1);
522 save->disp2_req_cntl2 = INREG(RS400_DISP2_REQ_CNTL2);
523 save->dmif_mem_cntl1 = INREG(RS400_DMIF_MEM_CNTL1);
524 save->disp1_req_cntl1 = INREG(RS400_DISP1_REQ_CNTL1);
530 RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
535 save->crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
536 save->crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
537 save->crtc_h_total_disp = INREG(RADEON_CRTC_H_TOTAL_DISP);
538 save->crtc_h_sync_strt_wid = INREG(RADEON_CRTC_H_SYNC_STRT_WID);
539 save->crtc_v_total_disp = INREG(RADEON_CRTC_V_TOTAL_DISP);
540 save->crtc_v_sync_strt_wid = INREG(RADEON_CRTC_V_SYNC_STRT_WID);
542 save->crtc_offset = INREG(RADEON_CRTC_OFFSET);
543 save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
544 save->crtc_pitch = INREG(RADEON_CRTC_PITCH);
545 save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL);
548 save->crtc_tile_x0_y0 = INREG(R300_CRTC_TILE_X0_Y0);
551 save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
552 save->dac2_cntl = INREG(RADEON_DAC_CNTL2);
553 save->disp_hw_debug = INREG (RADEON_DISP_HW_DEBUG);
554 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
558 if (save->crtc_ext_cntl & RADEON_CRTC_DISPLAY_DIS)
567 RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save)
572 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
573 save->crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP);
574 save->crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID);
575 save->crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP);
576 save->crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID);
578 save->crtc2_offset = INREG(RADEON_CRTC2_OFFSET);
579 save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL);
580 save->crtc2_pitch = INREG(RADEON_CRTC2_PITCH);
583 save->crtc2_tile_x0_y0 = INREG(R300_CRTC2_TILE_X0_Y0);
585 save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID);
586 save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID);
588 save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL);
591 if (save->crtc2_gen_cntl & RADEON_CRTC2_DISP_DIS)
600 RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
602 save->ppll_ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV);
603 save->ppll_div_3 = INPLL(pScrn, RADEON_PPLL_DIV_3);
604 save->htotal_cntl = INPLL(pScrn, RADEON_HTOTAL_CNTL);
605 save->vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
609 save->ppll_ref_div,
610 save->ppll_div_3,
611 (unsigned)save->htotal_cntl);
614 save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
615 save->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
616 (save->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
621 RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save)
623 save->p2pll_ref_div = INPLL(pScrn, RADEON_P2PLL_REF_DIV);
624 save->p2pll_div_0 = INPLL(pScrn, RADEON_P2PLL_DIV_0);
625 save->htotal_cntl2 = INPLL(pScrn, RADEON_HTOTAL2_CNTL);
626 save->pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
630 (unsigned)save->p2pll_ref_div,
631 (unsigned)save->p2pll_div_0,
632 (unsigned)save->htotal_cntl2);
635 (unsigned)(save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK),
636 (unsigned)(save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK),
637 (unsigned)((save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK)
708 RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info)
710 save->ovr_clr = 0;
711 save->ovr_wid_left_right = 0;
712 save->ovr_wid_top_bottom = 0;
713 save->ov0_scale_cntl = 0;
714 save->subpic_cntl = 0;
715 save->viph_control = 0;
716 save->i2c_cntl_1 = 0;
717 save->rbbm_soft_reset = 0;
718 save->cap0_trig_cntl = 0;
719 save->cap1_trig_cntl = 0;
720 save->bus_cntl = info->BusCntl;
724 save->disp2_req_cntl1 = info->SavedReg->disp2_req_cntl1;
725 save->disp2_req_cntl2 = info->SavedReg->disp2_req_cntl2;
726 save->dmif_mem_cntl1 = info->SavedReg->dmif_mem_cntl1;
727 save->disp1_req_cntl1 = info->SavedReg->disp1_req_cntl1;
734 if (save->bus_cntl & (RADEON_BUS_READ_BURST))
735 save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN;
739 RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save)
741 save->surface_cntl = 0;
749 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
750 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
754 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
755 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
763 RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save,
774 save->crtc_offset = pScrn->fbOffset;
777 save->crtc_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL;
780 save->crtc_offset_cntl = 0;
784 save->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
788 save->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
792 save->crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
796 save->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
807 save->crtc_tile_x0_y0 = x | (y << 16);
816 /*save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL) & ~0xf;*/
822 save->crtc_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
829 save->crtc_offset_cntl = save->crtc_offset_cntl | (y % 16);
873 save->crtc_offset = Base;
879 RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
903 /*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/
904 save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
919 save->crtc_gen_cntl |= RADEON_CRTC_EN;
921 save->crtc_ext_cntl |= (RADEON_XCRT_CNT_EN|
926 save->disp_merge_cntl = info->SavedReg->disp_merge_cntl;
927 save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
929 save->crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0x3ff)
937 save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
944 save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
950 save->crtc_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
956 save->crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) +
959 save->crtc_pitch |= save->crtc_pitch << 16;
962 save->dac2_cntl = info->SavedReg->dac2_cntl;
963 save->tv_dac_cntl = info->SavedReg->tv_dac_cntl;
964 save->crtc2_gen_cntl = info->SavedReg->crtc2_gen_cntl;
965 save->disp_hw_debug = info->SavedReg->disp_hw_debug;
967 save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
968 save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
973 save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
974 save->tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
975 save->tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
983 RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save,
996 save->crtc2_offset = pScrn->fbOffset;
999 save->crtc2_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL;
1002 save->crtc2_offset_cntl = 0;
1006 save->crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
1010 save->crtc2_offset_cntl |= RADEON_CRTC_TILE_EN;
1014 save->crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
1018 save->crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN;
1029 save->crtc2_tile_x0_y0 = x | (y << 16);
1038 /*save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & ~0xf;*/
1044 save->crtc2_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
1051 save->crtc2_offset_cntl = save->crtc_offset_cntl | (y % 16);
1089 save->crtc2_offset = Base;
1096 RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
1120 save->crtc2_h_total_disp =
1128 save->crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
1135 save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
1141 save->crtc2_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
1147 save->crtc2_pitch = ((pScrn->displayWidth * pScrn->bitsPerPixel) +
1149 save->crtc2_pitch |= save->crtc2_pitch << 16;
1152 if (save->crtc2_gen_cntl & RADEON_CRTC2_CRT2_ON)
1153 save->crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
1155 save->crtc2_gen_cntl = 0;
1157 save->crtc2_gen_cntl |= ((format << 8)
1174 save->crtc2_gen_cntl |= RADEON_CRTC2_EN;
1176 save->disp2_merge_cntl = info->SavedReg->disp2_merge_cntl;
1177 save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN);
1179 save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
1180 save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid;
1188 RADEONInitPLLRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
1223 save->ppll_ref_div = info->RefDivider;
1224 save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16);
1225 save->htotal_cntl = 0;
1243 save->pll_output_freq = freq;
1247 save->dot_clock_freq = freq;
1248 save->feedback_div = feedback_div;
1249 save->reference_div = reference_div;
1250 save->post_div = post_divider;
1254 (unsigned)save->dot_clock_freq,
1255 (unsigned)save->pll_output_freq,
1256 save->feedback_div,
1257 save->reference_div,
1258 save->post_div);
1260 save->ppll_ref_div = save->reference_div;
1266 save->ppll_div_3 = 0x000600ad;
1269 save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
1271 save->htotal_cntl = mode->HTotal & 0x7;
1273 save->vclk_ecp_cntl = (info->SavedReg->vclk_ecp_cntl &
1279 RADEONInitPLL2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
1312 save->p2pll_ref_div = info->RefDivider;
1313 save->p2pll_div_0 = info->FeedbackDivider | (info->PostDivider << 16);
1314 save->htotal_cntl2 = 0;
1332 save->pll_output_freq_2 = freq;
1336 save->dot_clock_freq_2 = freq;
1337 save->feedback_div_2 = feedback_div;
1338 save->reference_div_2 = reference_div;
1339 save->post_div_2 = post_divider;
1343 (unsigned)save->dot_clock_freq_2,
1344 (unsigned)save->pll_output_freq_2,
1345 save->feedback_div_2,
1346 save->reference_div_2,
1347 save->post_div_2);
1349 save->p2pll_ref_div = save->reference_div_2;
1351 save->p2pll_div_0 = (save->feedback_div_2 |
1354 save->htotal_cntl2 = mode->HTotal & 0x7;
1356 save->pixclks_cntl = ((info->SavedReg->pixclks_cntl &
Indexes created Mon Apr 20 00:23:12 UTC 2026