Lines Matching refs:save
362 RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
367 save->dac_cntl = INREG(RADEON_DAC_CNTL);
368 save->dac2_cntl = INREG(RADEON_DAC_CNTL2);
369 save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
370 save->disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL);
371 save->disp_tv_out_cntl = INREG(RADEON_DISP_TV_OUT_CNTL);
372 save->disp_hw_debug = INREG(RADEON_DISP_HW_DEBUG);
373 save->dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL);
374 save->gpiopad_a = INREG(RADEON_GPIOPAD_A);
380 RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
385 save->fp_gen_cntl = INREG(RADEON_FP_GEN_CNTL);
386 save->fp2_gen_cntl = INREG (RADEON_FP2_GEN_CNTL);
387 save->fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH);
388 save->fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH);
389 save->fp_horz_vert_active = INREG(RADEON_FP_HORZ_VERT_ACTIVE);
390 save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL);
391 save->lvds_gen_cntl = INREG(RADEON_LVDS_GEN_CNTL);
392 save->lvds_pll_cntl = INREG(RADEON_LVDS_PLL_CNTL);
393 save->tmds_pll_cntl = INREG(RADEON_TMDS_PLL_CNTL);
394 save->tmds_transmitter_cntl= INREG(RADEON_TMDS_TRANSMITTER_CNTL);
396 save->fp_h_sync_strt_wid = INREG(RADEON_FP_H_SYNC_STRT_WID);
397 save->fp_v_sync_strt_wid = INREG(RADEON_FP_V_SYNC_STRT_WID);
398 save->fp_crtc_h_total_disp = INREG(RADEON_FP_CRTC_H_TOTAL_DISP);
399 save->fp_crtc_v_total_disp = INREG(RADEON_FP_CRTC_V_TOTAL_DISP);
403 save->tmds_pll_cntl ^= (1 << 22);
408 save->fp_2nd_gen_cntl = INREG(RS400_FP_2ND_GEN_CNTL);
409 save->fp2_2_gen_cntl = INREG(RS400_FP2_2_GEN_CNTL);
410 save->tmds2_cntl = INREG(RS400_TMDS2_CNTL);
411 save->tmds2_transmitter_cntl = INREG(RS400_TMDS2_TRANSMITTER_CNTL);
894 RADEONSavePtr save = info->ModeReg;
923 save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
924 save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
932 save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
938 save->fp_2nd_gen_cntl |= (RS400_FP_2ND_ON |
948 save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
949 save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
956 save->fp2_2_gen_cntl |= (RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN);
957 save->fp2_2_gen_cntl &= ~RS400_FP2_2_BLANK_EN;
965 save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
981 save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
986 save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1029 save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
1030 save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
1042 save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
1048 save->fp_2nd_gen_cntl &= ~(RS400_FP_2ND_ON |
1058 save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1059 save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
1066 save->fp2_2_gen_cntl &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN);
1067 save->fp2_2_gen_cntl |= RS400_FP2_2_BLANK_EN;
1075 save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
1091 save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1096 save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1108 RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
1139 save->tmds_pll_cntl = tmp;
1141 save->tmds_pll_cntl = info->SavedReg->tmds_pll_cntl & 0xfff00000;
1142 save->tmds_pll_cntl |= tmp;
1144 } else save->tmds_pll_cntl = tmp;
1146 save->tmds_transmitter_cntl = info->SavedReg->tmds_transmitter_cntl &
1150 save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
1152 save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
1154 save->fp_gen_cntl = info->SavedReg->fp_gen_cntl |
1158 save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
1160 save->fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
1169 save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
1171 save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
1175 save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1177 save->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1179 save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1181 save->fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
1184 save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1185 save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
1187 save->fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
1192 save->tmds2_transmitter_cntl = info->SavedReg->tmds2_transmitter_cntl &
1194 save->tmds2_transmitter_cntl &= ~(RS400_TMDS2_PLLEN);
1196 save->fp_2nd_gen_cntl = info->SavedReg->fp_2nd_gen_cntl;
1199 save->fp_2nd_gen_cntl |= RS400_PANEL_FORMAT_2ND; /* 24 bit format */
1201 save->fp_2nd_gen_cntl &= ~RS400_PANEL_FORMAT_2ND;/* 18 bit format */
1203 save->fp_2nd_gen_cntl &= ~RS400_FP_2ND_SOURCE_SEL_MASK;
1207 save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_RMX;
1209 save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_CRTC1;
1211 save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_CRTC2;
1217 RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save,
1225 save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl |
1228 save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
1231 save->fp2_gen_cntl &= ~(RADEON_FP2_ON |
1241 save->fp2_gen_cntl |= R200_FP2_DVO_CLOCK_MODE_SINGLE; /* Dell Inspiron 8600 */
1243 save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R200_FP2_DVO_CLOCK_MODE_SINGLE;
1255 save->fp2_gen_cntl |= R200_FP2_DVO_RATE_SEL_SDR;
1257 save->fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;
1263 save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
1265 save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
1267 save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
1269 save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
1272 save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
1273 save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1275 save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
1281 save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl |
1284 save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl &
1287 save->fp2_2_gen_cntl &= ~(RS400_FP2_2_ON |
1293 save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_RMX;
1295 save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_CRTC1;
1297 save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_CRTC2;
1303 RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save,
1310 save->lvds_pll_cntl = (info->SavedReg->lvds_pll_cntl |
1313 save->lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
1315 save->lvds_gen_cntl = info->SavedReg->lvds_gen_cntl;
1316 save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
1317 save->lvds_gen_cntl &= ~(RADEON_LVDS_ON |
1323 save->lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
1328 save->lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
1330 save->lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
1333 save->lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
1335 save->lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
1341 RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save,
1356 save->fp_vert_stretch = info->SavedReg->fp_vert_stretch &
1359 save->fp_horz_stretch = info->SavedReg->fp_horz_stretch &
1363 save->crtc_more_cntl = 0;
1369 save->crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
1373 save->fp_crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0x3ff)
1381 save->fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
1387 save->fp_crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff)
1393 save->fp_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff)
1399 save->fp_horz_vert_active = 0;
1421 save->fp_horz_stretch |= ((xres/8-1)<<16);
1424 inc = (save->fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
1427 save->fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
1435 save->fp_vert_stretch |= ((yres-1)<<12);
1438 inc = (save->fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
1441 save->fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
1451 save->crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
1458 save->fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
1466 save->fp_h_sync_strt_wid = ((((mode->CrtcHSyncStart - mode->CrtcHBlankStart) / 8) & 0x1fff)
1472 save->fp_crtc_v_total_disp = (((mode->CrtcVBlankEnd - mode->CrtcVBlankStart) & 0xffff)
1479 save->fp_v_sync_strt_wid = ((((mode->CrtcVSyncStart - mode->CrtcVBlankStart) & 0xfff)
1485 save->fp_horz_vert_active = (((native_mode->PanelYRes) & 0xfff) |
1493 RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save,
1501 save->disp_output_cntl = info->SavedReg->disp_output_cntl &
1504 save->dac2_cntl = info->SavedReg->dac2_cntl & ~(RADEON_DAC2_DAC_CLK_SEL);
1508 save->disp_output_cntl = info->SavedReg->disp_output_cntl &
1510 save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
1512 save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC_CLK_SEL;
1515 save->dac_cntl = (RADEON_DAC_MASK_ALL
1519 save->dac_macro_cntl = info->SavedReg->dac_macro_cntl;
1523 RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save)
1540 save->tv_dac_cntl = info->SavedReg->tv_dac_cntl &
1549 save->tv_dac_cntl = info->SavedReg->tv_dac_cntl &
1558 save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1566 RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save,
1573 RADEONInitTvDacCntl(output, save);
1576 save->gpiopad_a = info->SavedReg->gpiopad_a | 1;
1578 save->dac2_cntl = info->SavedReg->dac2_cntl | RADEON_DAC2_DAC2_CLK_SEL;
1582 save->disp_output_cntl = info->SavedReg->disp_output_cntl &
1584 save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1586 save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
1590 save->disp_hw_debug = info->SavedReg->disp_hw_debug | RADEON_CRT2_DISP1_SEL;
1594 save->disp_output_cntl = info->SavedReg->disp_output_cntl &
1596 save->disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1598 save->fp2_gen_cntl = info->SavedReg->fp2_gen_cntl &
1601 save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1603 save->disp_hw_debug = info->SavedReg->disp_hw_debug &
1700 /* save the regs we need */
1772 /* save the regs we need */
1863 /* save the regs we need */
1965 /* save the regs we need */
2044 /* save the regs we need */
Indexes created Thu Apr 23 00:23:13 UTC 2026