Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/r600

Lines Matching defs:dst_obj
105 	memcpy(&accel_state->dst_obj, dst, sizeof(struct r600_accel_object));
113 		accel_state->dst_obj.tiling_flags = 0;
115 	if (accel_state->dst_obj.pitch & pitch_align)
116 	    RADEON_FALLBACK(("Bad dst pitch 0x%08x\n", accel_state->dst_obj.pitch));
118 	if (accel_state->dst_obj.offset & base_align)
119 	    RADEON_FALLBACK(("Bad dst offset 0x%08x\n", accel_state->dst_obj.offset));
121 	memset(&accel_state->dst_obj, 0, sizeof(struct r600_accel_object));
149 	if (accel_state->dst_obj.bo)
150 	    radeon_cs_space_add_persistent_bo(info->cs, accel_state->dst_obj.bo,
151 					      0, accel_state->dst_obj.domain);
221     r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
222     r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
223     r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
244     cb_conf.w = accel_state->dst_obj.pitch;
245     cb_conf.h = accel_state->dst_obj.height;
246     cb_conf.base = accel_state->dst_obj.offset;
247     cb_conf.bo = accel_state->dst_obj.bo;
250         cb_conf.surface = accel_state->dst_obj.surface;
253     if (accel_state->dst_obj.bpp == 8) {
256     } else if (accel_state->dst_obj.bpp == 16) {
281     if (accel_state->dst_obj.tiling_flags == 0)
283     r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
288     if (accel_state->dst_obj.bpp == 16) {
296     } else if (accel_state->dst_obj.bpp == 8) {
397     r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
398     r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
399     r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
475     cb_conf.w = accel_state->dst_obj.pitch;
476     cb_conf.h = accel_state->dst_obj.height;
477     cb_conf.base = accel_state->dst_obj.offset;
478     cb_conf.bo = accel_state->dst_obj.bo;
481         cb_conf.surface = accel_state->dst_obj.surface;
483     if (accel_state->dst_obj.bpp == 8) {
486     } else if (accel_state->dst_obj.bpp == 16) {
506     if (accel_state->dst_obj.tiling_flags == 0)
508     r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
575     struct r600_accel_object src_obj, dst_obj;
584     dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
592 	dst_obj.offset = 0;
594 	dst_obj.bo = radeon_get_pixmap_bo(pDst);
595 	dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
598 	dst_obj.surface = radeon_get_pixmap_surface(pDst);
605 	dst_obj.offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset;
609 	dst_obj.bo = NULL;
617     dst_obj.width = pDst->drawable.width;
618     dst_obj.height = pDst->drawable.height;
619     dst_obj.bpp = pDst->drawable.bitsPerPixel;
620     dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
625 			   &dst_obj,
633 	    unsigned long size = accel_state->dst_obj.surface->bo_size;
634 	    unsigned long align = accel_state->dst_obj.surface->bo_alignment;
658 	    unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8;
731 	uint32_t orig_dst_domain = accel_state->dst_obj.domain;
734 	uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
735 	struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
750 	accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
751 	accel_state->dst_obj.bo = accel_state->copy_area_bo;
752 	accel_state->dst_obj.offset = tmp_offset;
753 	accel_state->dst_obj.tiling_flags = 0;
764 	accel_state->dst_obj.domain = orig_dst_domain;
765 	accel_state->dst_obj.bo = orig_bo;
766 	accel_state->dst_obj.offset = orig_offset;
767 	accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
1282     struct r600_accel_object src_obj, mask_obj, dst_obj;
1296 	dst_obj.offset = 0;
1297 	dst_obj.bo = radeon_get_pixmap_bo(pDst);
1299 	dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
1301 	dst_obj.surface = radeon_get_pixmap_surface(pDst);
1307 	dst_obj.offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset;
1309 	dst_obj.bo = NULL;
1312     dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
1319     dst_obj.width = pDst->drawable.width;
1320     dst_obj.height = pDst->drawable.height;
1321     dst_obj.bpp = pDst->drawable.bitsPerPixel;
1322     dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
1356 			       &dst_obj,
1376 			       &dst_obj,
1402     r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1403     r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1404     r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1446     cb_conf.w = accel_state->dst_obj.pitch;
1447     cb_conf.h = accel_state->dst_obj.height;
1448     cb_conf.base = accel_state->dst_obj.offset;
1450     cb_conf.bo = accel_state->dst_obj.bo;
1453         cb_conf.surface = accel_state->dst_obj.surface;
1487     if (accel_state->dst_obj.tiling_flags == 0)
1490     switch (dst_obj.bpp) {
1501     r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
1651     struct r600_accel_object scratch_obj, dst_obj;
1675     dst_obj.pitch = dst_pitch;
1676     dst_obj.width = dst_width;
1677     dst_obj.height = dst_height;
1678     dst_obj.offset = dst_mc_addr;
1679     dst_obj.bo = NULL;
1680     dst_obj.bpp = bpp;
1681     dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
1686 			   &dst_obj,
1821 	    info->accel_state->dst_obj.height = hpass;
1822 	    info->accel_state->dst_obj.offset = scratch_mc_addr + scratch_offset;
1867     struct r600_accel_object src_obj, dst_obj;
1907     dst_obj.pitch = dst_pitch_hw;
1908     dst_obj.width = pDst->drawable.width;
1909     dst_obj.height = pDst->drawable.height;
1910     dst_obj.offset = 0;
1911     dst_obj.bpp = bpp;
1912     dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
1913     dst_obj.bo = radeon_get_pixmap_bo(pDst);
1914     dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
1915     dst_obj.surface = radeon_get_pixmap_surface(pDst);
1920 			   &dst_obj,
1984     struct r600_accel_object src_obj, dst_obj;
2027     accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
2028     radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, accel_state->dst_obj.domain);
2044     dst_obj.pitch = scratch_pitch;
2045     dst_obj.width = w;
2046     dst_obj.height = h;
2047     dst_obj.offset = 0;
2048     dst_obj.bo = scratch;
2049     dst_obj.bpp = bpp;
2050     dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
2051     dst_obj.tiling_flags = 0;
2052     dst_obj.surface = NULL;
2057 			   &dst_obj,
2365     info->accel_state->dst_obj.bo = NULL;