Lines Matching refs:accel_state
55 struct radeon_accel_state *accel_state = info->accel_state;
62 memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object));
63 accel_state->src_size[0] = src0->pitch * src0->height * (src0->bpp/8);
66 accel_state->src_size[0] = src0->surface->bo_size;
71 if (accel_state->src_obj[0].pitch & pitch_align)
72 RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[0].pitch));
75 if (accel_state->src_obj[0].offset & base_align)
76 RADEON_FALLBACK(("Bad src offset 0x%08x\n", accel_state->src_obj[0].offset));
79 memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object));
80 accel_state->src_size[0] = 0;
84 memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object));
85 accel_state->src_size[1] = src1->pitch * src1->height * (src1->bpp/8);
88 accel_state->src_size[1] = src1->surface->bo_size;
93 if (accel_state->src_obj[1].pitch & pitch_align)
94 RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[1].pitch));
97 if (accel_state->src_obj[1].offset & base_align)
98 RADEON_FALLBACK(("Bad src offset 0x%08x\n", accel_state->src_obj[1].offset));
100 memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object));
101 accel_state->src_size[1] = 0;
105 memcpy(&accel_state->dst_obj, dst, sizeof(struct r600_accel_object));
106 accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8);
109 accel_state->dst_size = dst->surface->bo_size;
113 accel_state->dst_obj.tiling_flags = 0;
115 if (accel_state->dst_obj.pitch & pitch_align)
116 RADEON_FALLBACK(("Bad dst pitch 0x%08x\n", accel_state->dst_obj.pitch));
118 if (accel_state->dst_obj.offset & base_align)
119 RADEON_FALLBACK(("Bad dst offset 0x%08x\n", accel_state->dst_obj.offset));
121 memset(&accel_state->dst_obj, 0, sizeof(struct r600_accel_object));
122 accel_state->dst_size = 0;
130 accel_state->rop = rop;
131 accel_state->planemask = planemask;
133 accel_state->vs_size = 512;
134 accel_state->ps_size = 512;
137 accel_state->vs_mc_addr = vs_offset;
138 accel_state->ps_mc_addr = ps_offset;
141 radeon_cs_space_add_persistent_bo(info->cs, accel_state->shaders_bo,
143 if (accel_state->src_obj[0].bo)
144 radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[0].bo,
145 accel_state->src_obj[0].domain, 0);
146 if (accel_state->src_obj[1].bo)
147 radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[1].bo,
148 accel_state->src_obj[1].domain, 0);
149 if (accel_state->dst_obj.bo)
150 radeon_cs_space_add_persistent_bo(info->cs, accel_state->dst_obj.bo,
151 0, accel_state->dst_obj.domain);
159 accel_state->vs_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset +
161 accel_state->ps_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset +
173 struct radeon_accel_state *accel_state = info->accel_state;
208 accel_state->solid_vs_offset, accel_state->solid_ps_offset,
216 radeon_vbo_check(pScrn, &accel_state->vbo, 16);
219 r600_set_default_state(pScrn, accel_state->ib);
221 r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
222 r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
223 r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
226 vs_conf.shader_addr = accel_state->vs_mc_addr;
227 vs_conf.shader_size = accel_state->vs_size;
230 vs_conf.bo = accel_state->shaders_bo;
231 r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
233 ps_conf.shader_addr = accel_state->ps_mc_addr;
234 ps_conf.shader_size = accel_state->ps_size;
240 ps_conf.bo = accel_state->shaders_bo;
241 r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
244 cb_conf.w = accel_state->dst_obj.pitch;
245 cb_conf.h = accel_state->dst_obj.height;
246 cb_conf.base = accel_state->dst_obj.offset;
247 cb_conf.bo = accel_state->dst_obj.bo;
250 cb_conf.surface = accel_state->dst_obj.surface;
253 if (accel_state->dst_obj.bpp == 8) {
256 } else if (accel_state->dst_obj.bpp == 16) {
272 if (accel_state->planemask & 0x000000ff)
274 if (accel_state->planemask & 0x0000ff00)
276 if (accel_state->planemask & 0x00ff0000)
278 if (accel_state->planemask & 0xff000000)
280 cb_conf.rop = accel_state->rop;
281 if (accel_state->dst_obj.tiling_flags == 0)
283 r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
285 r600_set_spi(pScrn, accel_state->ib, 0, 0);
288 if (accel_state->dst_obj.bpp == 16) {
296 } else if (accel_state->dst_obj.bpp == 8) {
312 r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps,
315 if (accel_state->vsync)
318 accel_state->dst_pix = pPix;
319 accel_state->fg = fg;
329 struct radeon_accel_state *accel_state = info->accel_state;
331 if (accel_state->vsync)
332 r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPix,
333 accel_state->vline_crtc,
334 accel_state->vline_y1,
335 accel_state->vline_y2);
345 struct radeon_accel_state *accel_state = info->accel_state;
350 R600DoneSolid(info->accel_state->dst_pix);
352 R600PrepareSolid(accel_state->dst_pix,
353 accel_state->rop,
354 accel_state->planemask,
355 accel_state->fg);
359 if (accel_state->vsync)
362 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 8);
373 radeon_vbo_commit(pScrn, &accel_state->vbo);
380 struct radeon_accel_state *accel_state = info->accel_state;
392 radeon_vbo_check(pScrn, &accel_state->vbo, 16);
395 r600_set_default_state(pScrn, accel_state->ib);
397 r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
398 r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
399 r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
402 vs_conf.shader_addr = accel_state->vs_mc_addr;
403 vs_conf.shader_size = accel_state->vs_size;
406 vs_conf.bo = accel_state->shaders_bo;
407 r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
409 ps_conf.shader_addr = accel_state->ps_mc_addr;
410 ps_conf.shader_size = accel_state->ps_size;
416 ps_conf.bo = accel_state->shaders_bo;
417 r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
421 tex_res.w = accel_state->src_obj[0].width;
422 tex_res.h = accel_state->src_obj[0].height;
423 tex_res.pitch = accel_state->src_obj[0].pitch;
426 tex_res.base = accel_state->src_obj[0].offset;
427 tex_res.mip_base = accel_state->src_obj[0].offset;
428 tex_res.size = accel_state->src_size[0];
429 tex_res.bo = accel_state->src_obj[0].bo;
430 tex_res.mip_bo = accel_state->src_obj[0].bo;
433 tex_res.surface = accel_state->src_obj[0].surface;
435 if (accel_state->src_obj[0].bpp == 8) {
441 } else if (accel_state->src_obj[0].bpp == 16) {
459 if (accel_state->src_obj[0].tiling_flags == 0)
461 r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
472 r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
475 cb_conf.w = accel_state->dst_obj.pitch;
476 cb_conf.h = accel_state->dst_obj.height;
477 cb_conf.base = accel_state->dst_obj.offset;
478 cb_conf.bo = accel_state->dst_obj.bo;
481 cb_conf.surface = accel_state->dst_obj.surface;
483 if (accel_state->dst_obj.bpp == 8) {
486 } else if (accel_state->dst_obj.bpp == 16) {
497 if (accel_state->planemask & 0x000000ff)
499 if (accel_state->planemask & 0x0000ff00)
501 if (accel_state->planemask & 0x00ff0000)
503 if (accel_state->planemask & 0xff000000)
505 cb_conf.rop = accel_state->rop;
506 if (accel_state->dst_obj.tiling_flags == 0)
508 r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
510 r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
525 struct radeon_accel_state *accel_state = info->accel_state;
527 if (accel_state->vsync)
528 r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPix,
529 accel_state->vline_crtc,
530 accel_state->vline_y1,
531 accel_state->vline_y2);
543 struct radeon_accel_state *accel_state = info->accel_state;
546 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
563 radeon_vbo_commit(pScrn, &accel_state->vbo);
574 struct radeon_accel_state *accel_state = info->accel_state;
587 accel_state->same_surface = FALSE;
600 accel_state->same_surface = TRUE;
607 accel_state->same_surface = TRUE;
626 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
630 if (accel_state->same_surface == TRUE) {
633 unsigned long size = accel_state->dst_obj.surface->bo_size;
634 unsigned long align = accel_state->dst_obj.surface->bo_alignment;
636 if (accel_state->copy_area_bo) {
637 radeon_bo_unref(accel_state->copy_area_bo);
638 accel_state->copy_area_bo = NULL;
640 accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, align,
643 if (accel_state->copy_area_bo == NULL)
646 radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo,
649 radeon_bo_unref(accel_state->copy_area_bo);
650 accel_state->copy_area_bo = NULL;
653 accel_state->copy_area = (void*)accel_state->copy_area_bo;
658 unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8;
660 if (accel_state->copy_area) {
661 exaOffscreenFree(pDst->drawable.pScreen, accel_state->copy_area);
662 accel_state->copy_area = NULL;
664 accel_state->copy_area = exaOffscreenAlloc(pDst->drawable.pScreen, size, 256, TRUE, NULL, NULL);
665 if (!accel_state->copy_area)
671 if (accel_state->vsync)
674 accel_state->dst_pix = pDst;
675 accel_state->src_pix = pSrc;
676 accel_state->xdir = xdir;
677 accel_state->ydir = ydir;
687 struct radeon_accel_state *accel_state = info->accel_state;
689 if (!accel_state->same_surface)
692 if (accel_state->copy_area) {
694 exaOffscreenFree(pDst->drawable.pScreen, accel_state->copy_area);
695 accel_state->copy_area = NULL;
708 struct radeon_accel_state *accel_state = info->accel_state;
710 if (accel_state->same_surface && (srcX == dstX) && (srcY == dstY))
715 R600DoneCopy(info->accel_state->dst_pix);
717 R600PrepareCopy(accel_state->src_pix,
718 accel_state->dst_pix,
719 accel_state->xdir,
720 accel_state->ydir,
721 accel_state->rop,
722 accel_state->planemask);
726 if (accel_state->vsync)
729 if (accel_state->same_surface && accel_state->copy_area) {
731 uint32_t orig_dst_domain = accel_state->dst_obj.domain;
732 uint32_t orig_src_domain = accel_state->src_obj[0].domain;
733 uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
734 uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
735 struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
736 int orig_rop = accel_state->rop;
745 tmp_offset = accel_state->copy_area->offset + info->fbLocation + pScrn->fbOffset;
750 accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
751 accel_state->dst_obj.bo = accel_state->copy_area_bo;
752 accel_state->dst_obj.offset = tmp_offset;
753 accel_state->dst_obj.tiling_flags = 0;
754 accel_state->rop = 3;
760 accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM;
761 accel_state->src_obj[0].bo = accel_state->copy_area_bo;
762 accel_state->src_obj[0].offset = tmp_offset;
763 accel_state->src_obj[0].tiling_flags = 0;
764 accel_state->dst_obj.domain = orig_dst_domain;
765 accel_state->dst_obj.bo = orig_bo;
766 accel_state->dst_obj.offset = orig_offset;
767 accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
768 accel_state->rop = orig_rop;
774 accel_state->src_obj[0].domain = orig_src_domain;
775 accel_state->src_obj[0].bo = orig_bo;
776 accel_state->src_obj[0].offset = orig_offset;
777 accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
945 struct radeon_accel_state *accel_state = info->accel_state;
972 tex_res.pitch = accel_state->src_obj[unit].pitch;
975 tex_res.base = accel_state->src_obj[unit].offset;
976 tex_res.mip_base = accel_state->src_obj[unit].offset;
977 tex_res.size = accel_state->src_size[unit];
979 tex_res.bo = accel_state->src_obj[unit].bo;
980 tex_res.mip_bo = accel_state->src_obj[unit].bo;
983 tex_res.surface = accel_state->src_obj[unit].surface;
988 switch (accel_state->src_obj[unit].bpp) {
1054 if (!accel_state->msk_pic) {
1064 if (accel_state->component_alpha) {
1065 if (accel_state->src_alpha) {
1092 if (accel_state->component_alpha) {
1117 if (accel_state->src_obj[unit].tiling_flags == 0)
1119 r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[unit].domain);
1162 r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
1165 accel_state->is_transform[unit] = TRUE;
1166 accel_state->transform[unit] = pPict->transform;
1178 accel_state->is_transform[unit] = FALSE;
1192 r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_vs + (unit * 2),
1278 struct radeon_accel_state *accel_state = info->accel_state;
1357 accel_state->comp_vs_offset, accel_state->comp_ps_offset,
1361 accel_state->msk_pic = pMaskPicture;
1363 accel_state->component_alpha = TRUE;
1365 accel_state->src_alpha = TRUE;
1367 accel_state->src_alpha = FALSE;
1369 accel_state->component_alpha = FALSE;
1370 accel_state->src_alpha = FALSE;
1377 accel_state->comp_vs_offset, accel_state->comp_ps_offset,
1381 accel_state->msk_pic = NULL;
1382 accel_state->component_alpha = FALSE;
1383 accel_state->src_alpha = FALSE;
1394 radeon_vbo_check(pScrn, &accel_state->vbo, 24);
1396 radeon_vbo_check(pScrn, &accel_state->vbo, 16);
1400 r600_set_default_state(pScrn, accel_state->ib);
1402 r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1403 r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1404 r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
1407 R600IBDiscard(pScrn, accel_state->ib);
1413 R600IBDiscard(pScrn, accel_state->ib);
1417 accel_state->is_transform[1] = FALSE;
1420 r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (1 << 0));
1421 r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0));
1423 r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (0 << 0));
1424 r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0));
1428 vs_conf.shader_addr = accel_state->vs_mc_addr;
1429 vs_conf.shader_size = accel_state->vs_size;
1432 vs_conf.bo = accel_state->shaders_bo;
1433 r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
1435 ps_conf.shader_addr = accel_state->ps_mc_addr;
1436 ps_conf.shader_size = accel_state->ps_size;
1442 ps_conf.bo = accel_state->shaders_bo;
1443 r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
1446 cb_conf.w = accel_state->dst_obj.pitch;
1447 cb_conf.h = accel_state->dst_obj.height;
1448 cb_conf.base = accel_state->dst_obj.offset;
1450 cb_conf.bo = accel_state->dst_obj.bo;
1453 cb_conf.surface = accel_state->dst_obj.surface;
1487 if (accel_state->dst_obj.tiling_flags == 0)
1501 r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
1504 r600_set_spi(pScrn, accel_state->ib, (2 - 1), 2);
1506 r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
1508 if (accel_state->vsync)
1511 accel_state->composite_op = op;
1512 accel_state->dst_pic = pDstPicture;
1513 accel_state->src_pic = pSrcPicture;
1514 accel_state->dst_pix = pDst;
1515 accel_state->msk_pix = pMask;
1516 accel_state->src_pix = pSrc;
1522 struct radeon_accel_state *accel_state)
1526 if (accel_state->vsync)
1527 r600_cp_wait_vline_sync(pScrn, accel_state->ib, pDst,
1528 accel_state->vline_crtc,
1529 accel_state->vline_y1,
1530 accel_state->vline_y2);
1532 vtx_size = accel_state->msk_pic ? 24 : 16;
1542 struct radeon_accel_state *accel_state = info->accel_state;
1544 R600FinishComposite(pScrn, pDst, accel_state);
1546 if (!accel_state->src_pic->pDrawable)
1547 pScreen->DestroyPixmap(accel_state->src_pix);
1549 if (accel_state->msk_pic && !accel_state->msk_pic->pDrawable)
1550 pScreen->DestroyPixmap(accel_state->msk_pix);
1561 struct radeon_accel_state *accel_state = info->accel_state;
1569 R600FinishComposite(pScrn, pDst, info->accel_state);
1571 R600PrepareComposite(info->accel_state->composite_op,
1572 info->accel_state->src_pic,
1573 info->accel_state->msk_pic,
1574 info->accel_state->dst_pic,
1575 info->accel_state->src_pix,
1576 info->accel_state->msk_pix,
1577 info->accel_state->dst_pix);
1581 if (accel_state->vsync)
1584 if (accel_state->msk_pic) {
1586 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 24);
1609 radeon_vbo_commit(pScrn, &accel_state->vbo);
1613 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
1630 radeon_vbo_commit(pScrn, &accel_state->vbo);
1643 struct radeon_accel_state *accel_state = info->accel_state;
1687 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
1717 info->accel_state->src_obj[0].height = oldhpass;
1718 info->accel_state->src_obj[0].offset = offset;
1752 struct radeon_accel_state *accel_state = info->accel_state;
1802 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
1821 info->accel_state->dst_obj.height = hpass;
1822 info->accel_state->dst_obj.offset = scratch_mc_addr + scratch_offset;
1852 struct radeon_accel_state *accel_state = info->accel_state;
1921 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
1950 if (info->accel_state->vsync)
1971 struct radeon_accel_state *accel_state = info->accel_state;
2023 radeon_cs_space_add_persistent_bo(info->cs, info->accel_state->shaders_bo,
2025 accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
2026 radeon_add_pixmap(info->cs, pSrc, info->accel_state->src_obj[0].domain, 0);
2027 accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
2028 radeon_cs_space_add_persistent_bo(info->cs, scratch, 0, accel_state->dst_obj.domain);
2058 accel_state->copy_vs_offset, accel_state->copy_ps_offset,
2105 struct radeon_accel_state *accel_state = info->accel_state;
2107 return ++accel_state->exaSyncMarker;
2116 struct radeon_accel_state *accel_state = info->accel_state;
2118 if (accel_state->exaMarkerSynced != marker) {
2125 accel_state->exaMarkerSynced = marker;
2134 struct radeon_accel_state *accel_state = info->accel_state;
2139 accel_state->shaders = NULL;
2144 accel_state->shaders_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
2146 if (accel_state->shaders_bo == NULL) {
2155 accel_state->shaders = exaOffscreenAlloc(pScreen, size, 256,
2158 if (accel_state->shaders == NULL)
2169 struct radeon_accel_state *accel_state = info->accel_state;
2177 ret = radeon_bo_map(accel_state->shaders_bo, 1);
2182 shader = accel_state->shaders_bo->ptr;
2186 shader = (pointer)((char *)info->FB + accel_state->shaders->offset);
2189 accel_state->solid_vs_offset = 0;
2190 R600_solid_vs(ChipSet, shader + accel_state->solid_vs_offset / 4);
2193 accel_state->solid_ps_offset = 512;
2194 R600_solid_ps(ChipSet, shader + accel_state->solid_ps_offset / 4);
2197 accel_state->copy_vs_offset = 1024;
2198 R600_copy_vs(ChipSet, shader + accel_state->copy_vs_offset / 4);
2201 accel_state->copy_ps_offset = 1536;
2202 R600_copy_ps(ChipSet, shader + accel_state->copy_ps_offset / 4);
2205 accel_state->comp_vs_offset = 2048;
2206 R600_comp_vs(ChipSet, shader + accel_state->comp_vs_offset / 4);
2209 accel_state->comp_ps_offset = 2560;
2210 R600_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4);
2213 accel_state->xv_vs_offset = 3072;
2214 R600_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4);
2217 accel_state->xv_ps_offset = 3584;
2218 R600_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4);
2223 radeon_bo_unmap(accel_state->shaders_bo);
2262 if (info->accel_state->exa == NULL) {
2267 info->accel_state->exa->exa_major = EXA_VERSION_MAJOR;
2268 info->accel_state->exa->exa_minor = EXA_VERSION_MINOR;
2270 info->accel_state->exa->PrepareSolid = R600PrepareSolid;
2271 info->accel_state->exa->Solid = R600Solid;
2272 info->accel_state->exa->DoneSolid = R600DoneSolid;
2274 info->accel_state->exa->PrepareCopy = R600PrepareCopy;
2275 info->accel_state->exa->Copy = R600Copy;
2276 info->accel_state->exa->DoneCopy = R600DoneCopy;
2278 info->accel_state->exa->MarkSync = R600MarkSync;
2279 info->accel_state->exa->WaitMarker = R600Sync;
2284 info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;
2285 info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
2286 info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
2287 info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;
2288 info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS;
2289 info->accel_state->exa->UploadToScreen = R600UploadToScreenCS;
2290 info->accel_state->exa->DownloadFromScreen = R600DownloadFromScreenCS;
2292 info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2;
2298 info->accel_state->exa->PrepareAccess = R600PrepareAccess;
2299 info->accel_state->exa->FinishAccess = R600FinishAccess;
2303 info->accel_state->exa->UploadToScreen = R600UploadToScreen;
2304 info->accel_state->exa->DownloadFromScreen = R600DownloadFromScreen;
2308 info->accel_state->exa->flags = EXA_OFFSCREEN_PIXMAPS;
2310 info->accel_state->exa->flags |= EXA_SUPPORTS_PREPARE_AUX;
2316 info->accel_state->exa->flags |= EXA_HANDLES_PIXMAPS;
2318 info->accel_state->exa->flags |= EXA_MIXED_PIXMAPS;
2323 info->accel_state->exa->pixmapOffsetAlign = 256;
2324 info->accel_state->exa->pixmapPitchAlign = 256;
2326 info->accel_state->exa->CheckComposite = R600CheckComposite;
2327 info->accel_state->exa->PrepareComposite = R600PrepareComposite;
2328 info->accel_state->exa->Composite = R600Composite;
2329 info->accel_state->exa->DoneComposite = R600DoneComposite;
2334 info->accel_state->exa->maxPitchBytes = 32768;
2335 info->accel_state->exa->maxX = 8192;
2337 info->accel_state->exa->maxX = 8192;
2339 info->accel_state->exa->maxY = 8192;
2344 info->accel_state->vsync = TRUE;
2346 info->accel_state->vsync = FALSE;
2348 if (!exaDriverInit(pScreen, info->accel_state->exa)) {
2349 free(info->accel_state->exa);
2361 info->accel_state->XInited3D = FALSE;
2362 info->accel_state->copy_area = NULL;
2363 info->accel_state->src_obj[0].bo = NULL;
2364 info->accel_state->src_obj[1].bo = NULL;
2365 info->accel_state->dst_obj.bo = NULL;
2366 info->accel_state->copy_area_bo = NULL;
2367 info->accel_state->vbo.vb_start_op = -1;
2368 info->accel_state->finish_op = r600_finish_op;
2369 info->accel_state->vbo.verts_per_op = 3;