Lines Matching refs:src_obj
62 memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object));
71 if (accel_state->src_obj[0].pitch & pitch_align)
72 RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[0].pitch));
75 if (accel_state->src_obj[0].offset & base_align)
76 RADEON_FALLBACK(("Bad src offset 0x%08x\n", accel_state->src_obj[0].offset));
79 memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object));
84 memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object));
93 if (accel_state->src_obj[1].pitch & pitch_align)
94 RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[1].pitch));
97 if (accel_state->src_obj[1].offset & base_align)
98 RADEON_FALLBACK(("Bad src offset 0x%08x\n", accel_state->src_obj[1].offset));
100 memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object));
143 if (accel_state->src_obj[0].bo)
144 radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[0].bo,
145 accel_state->src_obj[0].domain, 0);
146 if (accel_state->src_obj[1].bo)
147 radeon_cs_space_add_persistent_bo(info->cs, accel_state->src_obj[1].bo,
148 accel_state->src_obj[1].domain, 0);
421 tex_res.w = accel_state->src_obj[0].width;
422 tex_res.h = accel_state->src_obj[0].height;
423 tex_res.pitch = accel_state->src_obj[0].pitch;
426 tex_res.base = accel_state->src_obj[0].offset;
427 tex_res.mip_base = accel_state->src_obj[0].offset;
429 tex_res.bo = accel_state->src_obj[0].bo;
430 tex_res.mip_bo = accel_state->src_obj[0].bo;
433 tex_res.surface = accel_state->src_obj[0].surface;
435 if (accel_state->src_obj[0].bpp == 8) {
441 } else if (accel_state->src_obj[0].bpp == 16) {
459 if (accel_state->src_obj[0].tiling_flags == 0)
461 r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
575 struct r600_accel_object src_obj, dst_obj;
585 src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
591 src_obj.offset = 0;
593 src_obj.bo = radeon_get_pixmap_bo(pSrc);
596 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
597 src_obj.surface = radeon_get_pixmap_surface(pSrc);
604 src_obj.offset = exaGetPixmapOffset(pSrc) + info->fbLocation + pScrn->fbOffset;
608 src_obj.bo = NULL;
612 src_obj.width = pSrc->drawable.width;
613 src_obj.height = pSrc->drawable.height;
614 src_obj.bpp = pSrc->drawable.bitsPerPixel;
615 src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
623 &src_obj,
732 uint32_t orig_src_domain = accel_state->src_obj[0].domain;
733 uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
760 accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM;
761 accel_state->src_obj[0].bo = accel_state->copy_area_bo;
762 accel_state->src_obj[0].offset = tmp_offset;
763 accel_state->src_obj[0].tiling_flags = 0;
774 accel_state->src_obj[0].domain = orig_src_domain;
775 accel_state->src_obj[0].bo = orig_bo;
776 accel_state->src_obj[0].offset = orig_offset;
777 accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
972 tex_res.pitch = accel_state->src_obj[unit].pitch;
975 tex_res.base = accel_state->src_obj[unit].offset;
976 tex_res.mip_base = accel_state->src_obj[unit].offset;
979 tex_res.bo = accel_state->src_obj[unit].bo;
980 tex_res.mip_bo = accel_state->src_obj[unit].bo;
983 tex_res.surface = accel_state->src_obj[unit].surface;
988 switch (accel_state->src_obj[unit].bpp) {
1117 if (accel_state->src_obj[unit].tiling_flags == 0)
1119 r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[unit].domain);
1282 struct r600_accel_object src_obj, mask_obj, dst_obj;
1295 src_obj.offset = 0;
1298 src_obj.bo = radeon_get_pixmap_bo(pSrc);
1300 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
1302 src_obj.surface = radeon_get_pixmap_surface(pSrc);
1306 src_obj.offset = exaGetPixmapOffset(pSrc) + info->fbLocation + pScrn->fbOffset;
1308 src_obj.bo = NULL;
1311 src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
1314 src_obj.width = pSrc->drawable.width;
1315 src_obj.height = pSrc->drawable.height;
1316 src_obj.bpp = pSrc->drawable.bitsPerPixel;
1317 src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
1354 &src_obj,
1374 &src_obj,
1717 info->accel_state->src_obj[0].height = oldhpass;
1718 info->accel_state->src_obj[0].offset = offset;
1764 struct r600_accel_object scratch_obj, src_obj;
1782 src_obj.pitch = src_pitch;
1783 src_obj.width = src_width;
1784 src_obj.height = src_height;
1785 src_obj.offset = src_mc_addr;
1786 src_obj.bo = NULL;
1787 src_obj.bpp = bpp;
1788 src_obj.domain = RADEON_GEM_DOMAIN_VRAM;
1799 &src_obj,
1867 struct r600_accel_object src_obj, dst_obj;
1897 src_obj.pitch = scratch_pitch;
1898 src_obj.width = w;
1899 src_obj.height = h;
1900 src_obj.offset = 0;
1901 src_obj.bpp = bpp;
1902 src_obj.domain = RADEON_GEM_DOMAIN_GTT;
1903 src_obj.bo = scratch;
1904 src_obj.tiling_flags = 0;
1905 src_obj.surface = NULL;
1918 &src_obj,
1984 struct r600_accel_object src_obj, dst_obj;
2025 accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM;
2026 radeon_add_pixmap(info->cs, pSrc, info->accel_state->src_obj[0].domain, 0);
2034 src_obj.pitch = src_pitch_hw;
2035 src_obj.width = pSrc->drawable.width;
2036 src_obj.height = pSrc->drawable.height;
2037 src_obj.offset = 0;
2038 src_obj.bpp = bpp;
2039 src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
2040 src_obj.bo = radeon_get_pixmap_bo(pSrc);
2041 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
2042 src_obj.surface = radeon_get_pixmap_surface(pSrc);
2055 &src_obj,
2363 info->accel_state->src_obj[0].bo = NULL;
2364 info->accel_state->src_obj[1].bo = NULL;