Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/r600

Lines Matching defs:shader
38 int R600_solid_vs(RADEONChipFamily ChipSet, uint32_t* shader)
43     shader[i++] = CF_DWORD0(ADDR(4));
44     shader[i++] = CF_DWORD1(POP_COUNT(0),
55     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0),
61     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
73     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0),
79     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
91     shader[i++] = 0x00000000;
92     shader[i++] = 0x00000000;
94     shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
102     shader[i++] = VTX_DWORD1_GPR(DST_GPR(1),
113     shader[i++] = VTX_DWORD2(OFFSET(0),
121     shader[i++] = VTX_DWORD_PAD;
127 int R600_solid_ps(RADEONChipFamily ChipSet, uint32_t* shader)
132     shader[i++] = CF_ALU_DWORD0(ADDR(2),
136     shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP),
145     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0),
151     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
164     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
175     shader[i++] = ALU_DWORD1_OP2(ChipSet,
190     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
201     shader[i++] = ALU_DWORD1_OP2(ChipSet,
216     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
227     shader[i++] = ALU_DWORD1_OP2(ChipSet,
242     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
253     shader[i++] = ALU_DWORD1_OP2(ChipSet,
272 int R600_copy_vs(RADEONChipFamily ChipSet, uint32_t* shader)
277     shader[i++] = CF_DWORD0(ADDR(4));
278     shader[i++] = CF_DWORD1(POP_COUNT(0),
289     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0),
295     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
307     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0),
313     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
325     shader[i++] = 0x00000000;
326     shader[i++] = 0x00000000;
328     shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
336     shader[i++] = VTX_DWORD1_GPR(DST_GPR(1),
347     shader[i++] = VTX_DWORD2(OFFSET(0),
355     shader[i++] = VTX_DWORD_PAD;
357     shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
365     shader[i++] = VTX_DWORD1_GPR(DST_GPR(0),
376     shader[i++] = VTX_DWORD2(OFFSET(8),
384     shader[i++] = VTX_DWORD_PAD;
390 int R600_copy_ps(RADEONChipFamily ChipSet, uint32_t* shader)
395     shader[i++] = CF_DWORD0(ADDR(2));
396     shader[i++] = CF_DWORD1(POP_COUNT(0),
407     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0),
413     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
425     shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
432     shader[i++] = TEX_DWORD1(DST_GPR(0),
443     shader[i++] = TEX_DWORD2(OFFSET_X(0),
451     shader[i++] = TEX_DWORD_PAD;
457  * ; xv vertex shader
467 int R600_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader)
472     shader[i++] = CF_DWORD0(ADDR(6));
473     shader[i++] = CF_DWORD1(POP_COUNT(0),
485     shader[i++] = CF_ALU_DWORD0(ADDR(4),
489     shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP),
499     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0),
505     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
517     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0),
523     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
537     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
548     shader[i++] = ALU_DWORD1_OP2(ChipSet,
564     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
575     shader[i++] = ALU_DWORD1_OP2(ChipSet,
591     shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
599     shader[i++] = VTX_DWORD1_GPR(DST_GPR(1),
610     shader[i++] = VTX_DWORD2(OFFSET(0),
618     shader[i++] = VTX_DWORD_PAD;
620     shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
628     shader[i++] = VTX_DWORD1_GPR(DST_GPR(0),
639     shader[i++] = VTX_DWORD2(OFFSET(8),
647     shader[i++] = VTX_DWORD_PAD;
652 int R600_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader)
657     shader[i++] = CF_DWORD0(ADDR(16));
658     shader[i++] = CF_DWORD1(POP_COUNT(0),
669     shader[i++] = CF_DWORD0(ADDR(24));
670     shader[i++] = CF_DWORD1(POP_COUNT(0),
681     shader[i++] = CF_ALU_DWORD0(ADDR(4),
685     shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP),
694     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0),
700     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
713     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
724     shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_CFILE_BASE + 0),
735     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
746     shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_CFILE_BASE + 0),
757     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 0),
768     shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(ALU_SRC_CFILE_BASE + 0),
779     shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0),
790     shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_1),
803     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1),
814     shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV),
825     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1),
836     shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV),
847     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 1),
858     shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV),
869     shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0),
880     shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_1),
892     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 2),
903     shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV),
914     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 2),
925     shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV),
936     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_CFILE_BASE + 2),
947     shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_PV),
958     shader[i++] = ALU_DWORD0(SRC0_SEL(SQ_ALU_SRC_0),
969     shader[i++] = ALU_DWORD1_OP3(SRC2_SEL(SQ_ALU_SRC_1),
981     shader[i++] = CF_DWORD0(ADDR(18));
982     shader[i++] = CF_DWORD1(POP_COUNT(0),
993     shader[i++] = CF_DWORD0(ADDR(0));
994     shader[i++] = CF_DWORD1(POP_COUNT(0),
1005     shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
1012     shader[i++] = TEX_DWORD1(DST_GPR(1),
1023     shader[i++] = TEX_DWORD2(OFFSET_X(0),
1031     shader[i++] = TEX_DWORD_PAD;
1033     shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
1040     shader[i++] = TEX_DWORD1(DST_GPR(1),
1051     shader[i++] = TEX_DWORD2(OFFSET_X(0),
1059     shader[i++] = TEX_DWORD_PAD;
1061     shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
1068     shader[i++] = TEX_DWORD1(DST_GPR(1),
1079     shader[i++] = TEX_DWORD2(OFFSET_X(0),
1087     shader[i++] = TEX_DWORD_PAD;
1089     shader[i++] = CF_DWORD0(ADDR(26));
1090     shader[i++] = CF_DWORD1(POP_COUNT(0),
1101     shader[i++] = CF_DWORD0(ADDR(0));
1102     shader[i++] = CF_DWORD1(POP_COUNT(0),
1113     shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
1120     shader[i++] = TEX_DWORD1(DST_GPR(1),
1131     shader[i++] = TEX_DWORD2(OFFSET_X(0),
1139     shader[i++] = TEX_DWORD_PAD;
1145 int R600_comp_vs(RADEONChipFamily ChipSet, uint32_t* shader)
1150     shader[i++] = CF_DWORD0(ADDR(3));
1151     shader[i++] = CF_DWORD1(POP_COUNT(0),
1162     shader[i++] = CF_DWORD0(ADDR(9));
1163     shader[i++] = CF_DWORD1(POP_COUNT(0),
1174     shader[i++] = CF_DWORD0(ADDR(0));
1175     shader[i++] = CF_DWORD1(POP_COUNT(0),
1186     shader[i++] = CF_DWORD0(ADDR(44));
1187     shader[i++] = CF_DWORD1(POP_COUNT(0),
1199     shader[i++] = CF_ALU_DWORD0(ADDR(14),
1203     shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP),
1213     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0),
1219     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
1231     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0),
1237     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
1249     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(1),
1255     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
1267     shader[i++] = CF_DWORD0(ADDR(0));
1268     shader[i++] = CF_DWORD1(POP_COUNT(0),
1279     shader[i++] = CF_DWORD0(ADDR(50));
1280     shader[i++] = CF_DWORD1(POP_COUNT(0),
1292     shader[i++] = CF_ALU_DWORD0(ADDR(34),
1296     shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP),
1306     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_POS0),
1312     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
1324     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(0),
1330     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
1342     shader[i++] = CF_DWORD0(ADDR(0));
1343     shader[i++] = CF_DWORD1(POP_COUNT(0),
1356     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
1367     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1383     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
1394     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1410     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
1421     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1437     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
1448     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1464     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
1475     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1491     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
1502     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1518     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
1529     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1545     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
1556     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1572     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
1583     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1599     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
1610     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1626     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
1637     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1653     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
1664     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1680     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
1691     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1707     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
1718     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1734     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
1745     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1761     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
1772     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1788     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 3),
1799     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1815     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 3),
1826     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1842     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 4),
1853     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1869     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 4),
1880     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1896     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
1907     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1923     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
1934     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1950     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
1961     shader[i++] = ALU_DWORD1_OP2(ChipSet,
1977     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
1988     shader[i++] = ALU_DWORD1_OP2(ChipSet,
2004     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
2015     shader[i++] = ALU_DWORD1_OP2(ChipSet,
2031     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
2042     shader[i++] = ALU_DWORD1_OP2(ChipSet,
2058     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
2069     shader[i++] = ALU_DWORD1_OP2(ChipSet,
2085     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 0),
2096     shader[i++] = ALU_DWORD1_OP2(ChipSet,
2112     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 2),
2123     shader[i++] = ALU_DWORD1_OP2(ChipSet,
2139     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 2),
2150     shader[i++] = ALU_DWORD1_OP2(ChipSet,
2166     shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
2174     shader[i++] = VTX_DWORD1_GPR(DST_GPR(2),
2185     shader[i++] = VTX_DWORD2(OFFSET(0),
2193     shader[i++] = VTX_DWORD_PAD;
2195     shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
2203     shader[i++] = VTX_DWORD1_GPR(DST_GPR(1),
2214     shader[i++] = VTX_DWORD2(OFFSET(8),
2222     shader[i++] = VTX_DWORD_PAD;
2224     shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
2232     shader[i++] = VTX_DWORD1_GPR(DST_GPR(0),
2243     shader[i++] = VTX_DWORD2(OFFSET(16),
2251     shader[i++] = VTX_DWORD_PAD;
2254     shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
2262     shader[i++] = VTX_DWORD1_GPR(DST_GPR(1),
2273     shader[i++] = VTX_DWORD2(OFFSET(0),
2281     shader[i++] = VTX_DWORD_PAD;
2283     shader[i++] = VTX_DWORD0(VTX_INST(SQ_VTX_INST_FETCH),
2291     shader[i++] = VTX_DWORD1_GPR(DST_GPR(0),
2302     shader[i++] = VTX_DWORD2(OFFSET(8),
2310     shader[i++] = VTX_DWORD_PAD;
2316 int R600_comp_ps(RADEONChipFamily ChipSet, uint32_t* shader)
2321     shader[i++] = CF_DWORD0(ADDR(3));
2322     shader[i++] = CF_DWORD1(POP_COUNT(0),
2333     shader[i++] = CF_DWORD0(ADDR(7));
2334     shader[i++] = CF_DWORD1(POP_COUNT(0),
2345     shader[i++] = CF_DWORD0(ADDR(0));
2346     shader[i++] = CF_DWORD1(POP_COUNT(0),
2358     shader[i++] = CF_DWORD0(ADDR(14));
2359     shader[i++] = CF_DWORD1(POP_COUNT(0),
2371     shader[i++] = CF_ALU_DWORD0(ADDR(10),
2375     shader[i++] = CF_ALU_DWORD1(KCACHE_MODE1(SQ_CF_KCACHE_NOP),
2385     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0),
2391     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
2403     shader[i++] = CF_DWORD0(ADDR(0));
2404     shader[i++] = CF_DWORD1(POP_COUNT(0),
2416     shader[i++] = CF_DWORD0(ADDR(18));
2417     shader[i++] = CF_DWORD1(POP_COUNT(0),
2428     shader[i++] = CF_ALLOC_IMP_EXP_DWORD0(ARRAY_BASE(CF_PIXEL_MRT0),
2434     shader[i++] = CF_ALLOC_IMP_EXP_DWORD1_SWIZ(SRC_SEL_X(SQ_SEL_X),
2446     shader[i++] = CF_DWORD0(ADDR(0));
2447     shader[i++] = CF_DWORD1(POP_COUNT(0),
2460     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
2471     shader[i++] = ALU_DWORD1_OP2(ChipSet,
2487     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
2498     shader[i++] = ALU_DWORD1_OP2(ChipSet,
2514     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
2525     shader[i++] = ALU_DWORD1_OP2(ChipSet,
2541     shader[i++] = ALU_DWORD0(SRC0_SEL(ALU_SRC_GPR_BASE + 1),
2552     shader[i++] = ALU_DWORD1_OP2(ChipSet,
2568     shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
2575     shader[i++] = TEX_DWORD1(DST_GPR(0),
2586     shader[i++] = TEX_DWORD2(OFFSET_X(0),
2594     shader[i++] = TEX_DWORD_PAD;
2596     shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
2603     shader[i++] = TEX_DWORD1(DST_GPR(1),
2614     shader[i++] = TEX_DWORD2(OFFSET_X(0),
2622     shader[i++] = TEX_DWORD_PAD;
2625     shader[i++] = TEX_DWORD0(TEX_INST(SQ_TEX_INST_SAMPLE),
2632     shader[i++] = TEX_DWORD1(DST_GPR(0),
2643     shader[i++] = TEX_DWORD2(OFFSET_X(0),
2651     shader[i++] = TEX_DWORD_PAD;