Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/r600_textured

Lines Matching refs:accel_state
64     struct radeon_accel_state *accel_state = info->accel_state;
203 			   accel_state->xv_vs_offset, accel_state->xv_ps_offset,
215     radeon_vbo_check(pScrn, &accel_state->vbo, 16);
218     r600_set_default_state(pScrn, accel_state->ib);
220     r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
221     r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
222     r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
228 	r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0));
233 	r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0));
238     vs_conf.shader_addr         = accel_state->vs_mc_addr;
239     vs_conf.shader_size         = accel_state->vs_size;
242     vs_conf.bo                  = accel_state->shaders_bo;
243     r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
245     ps_conf.shader_addr         = accel_state->ps_mc_addr;
246     ps_conf.shader_size         = accel_state->ps_size;
252     ps_conf.bo                  = accel_state->shaders_bo;
253     r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
256     r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps,
263 	accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
267 	tex_res.w                   = accel_state->src_obj[0].width;
268 	tex_res.h                   = accel_state->src_obj[0].height;
269 	tex_res.pitch               = accel_state->src_obj[0].pitch;
272 	tex_res.base                = accel_state->src_obj[0].offset;
273 	tex_res.mip_base            = accel_state->src_obj[0].offset;
274 	tex_res.size                = accel_state->src_size[0];
275 	tex_res.bo                  = accel_state->src_obj[0].bo;
276 	tex_res.mip_bo              = accel_state->src_obj[0].bo;
293 	if (accel_state->src_obj[0].tiling_flags == 0)
295 	r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
309 	r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
314 	tex_res.w                   = accel_state->src_obj[0].width >> 1;
315 	tex_res.h                   = accel_state->src_obj[0].height >> 1;
316 	tex_res.pitch               = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
323 	tex_res.base                = accel_state->src_obj[0].offset + pPriv->planev_offset;
324 	tex_res.mip_base            = accel_state->src_obj[0].offset + pPriv->planev_offset;
326 	if (accel_state->src_obj[0].tiling_flags == 0)
328 	r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
332 	r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
337 	tex_res.w                   = accel_state->src_obj[0].width >> 1;
338 	tex_res.h                   = accel_state->src_obj[0].height >> 1;
339 	tex_res.pitch               = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
346 	tex_res.base                = accel_state->src_obj[0].offset + pPriv->planeu_offset;
347 	tex_res.mip_base            = accel_state->src_obj[0].offset + pPriv->planeu_offset;
349 	if (accel_state->src_obj[0].tiling_flags == 0)
351 	r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
355 	r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
360 	accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
364 	tex_res.w                   = accel_state->src_obj[0].width;
365 	tex_res.h                   = accel_state->src_obj[0].height;
366 	tex_res.pitch               = accel_state->src_obj[0].pitch >> 1;
369 	tex_res.base                = accel_state->src_obj[0].offset;
370 	tex_res.mip_base            = accel_state->src_obj[0].offset;
371 	tex_res.size                = accel_state->src_size[0];
372 	tex_res.bo                  = accel_state->src_obj[0].bo;
373 	tex_res.mip_bo              = accel_state->src_obj[0].bo;
389 	if (accel_state->src_obj[0].tiling_flags == 0)
391 	r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain);
405 	r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
411     cb_conf.w = accel_state->dst_obj.pitch;
412     cb_conf.h = accel_state->dst_obj.height;
413     cb_conf.base = accel_state->dst_obj.offset;
414     cb_conf.bo = accel_state->dst_obj.bo;
417         cb_conf.surface = accel_state->dst_obj.surface;
420     switch (accel_state->dst_obj.bpp) {
448     if (accel_state->dst_obj.tiling_flags == 0)
450     r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
452     r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
460     r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_vs,
474 	    r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPixmap,
501 	vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
518 	radeon_vbo_commit(pScrn, &accel_state->vbo);