Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/r6xx

Lines Matching defs:cb_conf
223 r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain)
231     if (info->cs && cb_conf->surface) {
232 	switch (cb_conf->surface->level[0].mode) {
243 	pitch = (cb_conf->surface->level[0].nblk_x >> 3) - 1;
244 	slice = ((cb_conf->surface->level[0].nblk_x * cb_conf->surface->level[0].nblk_y) / 64) - 1;
248 	array_mode = cb_conf->array_mode;
249 	pitch = (cb_conf->w / 8) - 1;
250 	h = RADEON_ALIGN(cb_conf->h, 8);
251 	slice = ((cb_conf->w * h) / 64) - 1;
254     cb_color_info = ((cb_conf->endian      << ENDIAN_shift)				|
255 		     (cb_conf->format      << CB_COLOR0_INFO__FORMAT_shift)		|
257 		     (cb_conf->number_type << NUMBER_TYPE_shift)			|
258 		     (cb_conf->comp_swap   << COMP_SWAP_shift)				|
259 		     (cb_conf->tile_mode   << CB_COLOR0_INFO__TILE_MODE_shift));
260     if (cb_conf->read_size)
262     if (cb_conf->blend_clamp)
264     if (cb_conf->clear_color)
266     if (cb_conf->blend_bypass)
268     if (cb_conf->blend_float32)
270     if (cb_conf->simple_float)
272     if (cb_conf->round_mode)
274     if (cb_conf->tile_compact)
276     if (cb_conf->source_format)
280     EREG(ib, (CB_COLOR0_BASE + (4 * cb_conf->id)), (cb_conf->base >> 8));
281     RELOC_BATCH(cb_conf->bo, 0, domain);
289         E32(ib, (2 << cb_conf->id));
297     EREG(ib, (CB_COLOR0_TILE + (4 * cb_conf->id)), (0     >> 8));	// CMASK per-tile data base/256
298     RELOC_BATCH(cb_conf->bo, 0, domain);
301     EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0     >> 8));	// FMASK per-tile data base/256
302     RELOC_BATCH(cb_conf->bo, 0, domain);
306     EREG(ib, (CB_COLOR0_SIZE + (4 * cb_conf->id)), ((pitch << PITCH_TILE_MAX_shift)	|
308     EREG(ib, (CB_COLOR0_VIEW + (4 * cb_conf->id)), ((0    << SLICE_START_shift)		|
310     EREG(ib, (CB_COLOR0_MASK + (4 * cb_conf->id)), ((0    << CMASK_BLOCK_MAX_shift)	|
315     EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
316     RELOC_BATCH(cb_conf->bo, 0, domain);
320     EREG(ib, CB_TARGET_MASK,          (cb_conf->pmask << TARGET0_ENABLE_shift));
321     cb_color_control = R600_ROP[cb_conf->rop] |
322 	(cb_conf->blend_enable << TARGET_BLEND_ENABLE_shift);
326 	EREG(ib, CB_BLEND_CONTROL,    cb_conf->blendcntl);
328 	if (cb_conf->blend_enable)
331 	EREG(ib, CB_BLEND0_CONTROL,   cb_conf->blendcntl);