Lines Matching refs:ib
68 void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib)
71 drmBufPtr buffer = ib;
108 void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib)
116 if (!ib) return;
118 ib->used = 0;
119 R600CPFlushIndirect(pScrn, ib);
123 r600_wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib)
129 PACK3(ib, IT_EVENT_WRITE, 1);
130 E32(ib, CACHE_FLUSH_AND_INV_EVENT);
132 EREG(ib, WAIT_UNTIL, (WAIT_3D_IDLE_bit |
138 r600_wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib)
143 EREG(ib, WAIT_UNTIL, WAIT_3D_IDLE_bit);
148 r600_start_3d(ScrnInfoPtr pScrn, drmBufPtr ib)
154 PACK3(ib, IT_START_3D_CMDBUF, 1);
155 E32(ib, 0);
159 PACK3(ib, IT_CONTEXT_CONTROL, 2);
160 E32(ib, 0x80000000);
161 E32(ib, 0x80000000);
172 r600_sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf)
212 PACK0(ib, SQ_CONFIG, 6);
213 E32(ib, sq_config);
214 E32(ib, sq_gpr_resource_mgmt_1);
215 E32(ib, sq_gpr_resource_mgmt_2);
216 E32(ib, sq_thread_resource_mgmt);
217 E32(ib, sq_stack_resource_mgmt_1);
218 E32(ib, sq_stack_resource_mgmt_2);
223 r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain)
280 EREG(ib, (CB_COLOR0_BASE + (4 * cb_conf->id)), (cb_conf->base >> 8));
288 PACK3(ib, IT_SURFACE_BASE_UPDATE, 1);
289 E32(ib, (2 << cb_conf->id));
297 EREG(ib, (CB_COLOR0_TILE + (4 * cb_conf->id)), (0 >> 8)); // CMASK per-tile data base/256
301 EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8)); // FMASK per-tile data base/256
306 EREG(ib, (CB_COLOR0_SIZE + (4 * cb_conf->id)), ((pitch << PITCH_TILE_MAX_shift) |
308 EREG(ib, (CB_COLOR0_VIEW + (4 * cb_conf->id)), ((0 << SLICE_START_shift) |
310 EREG(ib, (CB_COLOR0_MASK + (4 * cb_conf->id)), ((0 << CMASK_BLOCK_MAX_shift) |
315 EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
320 EREG(ib, CB_TARGET_MASK, (cb_conf->pmask << TARGET0_ENABLE_shift));
325 EREG(ib, CB_COLOR_CONTROL, cb_color_control);
326 EREG(ib, CB_BLEND_CONTROL, cb_conf->blendcntl);
330 EREG(ib, CB_COLOR_CONTROL, cb_color_control);
331 EREG(ib, CB_BLEND0_CONTROL, cb_conf->blendcntl);
337 r600_cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type,
349 PACK3(ib, IT_SURFACE_SYNC, 4);
350 E32(ib, sync_type);
351 E32(ib, cp_coher_size);
352 E32(ib, (mc_addr >> 8));
353 E32(ib, 10); /* poll interval */
360 r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
400 EREG(ib, AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */
405 PACK3(ib, IT_WAIT_REG_MEM, 6);
406 E32(ib, IT_WAIT_REG | IT_WAIT_EQ);
407 E32(ib, IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS));
408 E32(ib, 0);
409 E32(ib, 0); // Ref value
410 E32(ib, AVIVO_D1MODE_VLINE_STAT); // Mask
411 E32(ib, 10); // Wait interval
413 PACK3(ib, IT_NOP, 1);
414 E32(ib, drmmode_crtc->mode_crtc->crtc_id);
423 EREG(ib, AVIVO_D1MODE_VLINE_START_END + radeon_crtc->crtc_offset,
428 PACK3(ib, IT_WAIT_REG_MEM, 6);
429 E32(ib, IT_WAIT_REG | IT_WAIT_EQ);
430 E32(ib, IT_WAIT_ADDR(AVIVO_D1MODE_VLINE_STATUS + radeon_crtc->crtc_offset));
431 E32(ib, 0);
432 E32(ib, 0); // Ref value
433 E32(ib, AVIVO_D1MODE_VLINE_STAT); // Mask
434 E32(ib, 10); // Wait interval
440 r600_set_spi(ScrnInfoPtr pScrn, drmBufPtr ib, int vs_export_count, int num_interp)
446 EREG(ib, SPI_VS_OUT_CONFIG, (vs_export_count << VS_EXPORT_COUNT_shift));
447 PACK0(ib, SPI_PS_IN_CONTROL_0, 3);
448 E32(ib, (num_interp << NUM_INTERP_shift));
449 E32(ib, 0);
450 E32(ib, 0);
455 r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain)
467 EREG(ib, SQ_PGM_START_FS, fs_conf->shader_addr >> 8);
472 EREG(ib, SQ_PGM_RESOURCES_FS, sq_pgm_resources);
473 EREG(ib, SQ_PGM_CF_OFFSET_FS, 0);
478 r600_vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain)
494 r600_cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit,
499 EREG(ib, SQ_PGM_START_VS, vs_conf->shader_addr >> 8);
504 EREG(ib, SQ_PGM_RESOURCES_VS, sq_pgm_resources);
505 EREG(ib, SQ_PGM_CF_OFFSET_VS, 0);
510 r600_ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain)
528 r600_cp_set_surface_sync(pScrn, ib, SH_ACTION_ENA_bit,
533 EREG(ib, SQ_PGM_START_PS, ps_conf->shader_addr >> 8);
538 EREG(ib, SQ_PGM_RESOURCES_PS, sq_pgm_resources);
539 EREG(ib, SQ_PGM_EXPORTS_PS, ps_conf->export_mode);
540 EREG(ib, SQ_PGM_CF_OFFSET_PS, 0);
545 r600_set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf)
552 PACK0(ib, SQ_ALU_CONSTANT + offset * SQ_ALU_CONSTANT_offset, countreg);
554 EFLOAT(ib, const_buf[i]);
559 r600_set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val)
566 EREG(ib, SQ_BOOL_CONST + offset * SQ_BOOL_CONST_offset, val);
571 r600_set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain)
597 r600_cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit,
602 r600_cp_set_surface_sync(pScrn, ib, VC_ACTION_ENA_bit,
608 PACK0(ib, SQ_VTX_RESOURCE + res->id * SQ_VTX_RESOURCE_offset, 7);
609 E32(ib, res->vb_addr & 0xffffffff); // 0: BASE_ADDRESS
610 E32(ib, (res->vtx_num_entries << 2) - 1); // 1: SIZE
611 E32(ib, sq_vtx_constant_word2); // 2: BASE_HI, STRIDE, CLAMP, FORMAT, ENDIAN
612 E32(ib, res->mem_req_size << MEM_REQUEST_SIZE_shift); // 3: MEM_REQUEST_SIZE ?!?
613 E32(ib, 0); // 4: n/a
614 E32(ib, 0); // 5: n/a
615 E32(ib, SQ_TEX_VTX_VALID_BUFFER << SQ_VTX_CONSTANT_WORD6_0__TYPE_shift); // 6: TYPE
621 r600_set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain)
696 r600_cp_set_surface_sync(pScrn, ib, TC_ACTION_ENA_bit,
701 PACK0(ib, SQ_TEX_RESOURCE + tex_res->id * SQ_TEX_RESOURCE_offset, 7);
702 E32(ib, sq_tex_resource_word0);
703 E32(ib, sq_tex_resource_word1);
704 E32(ib, ((tex_res->base) >> 8));
705 E32(ib, ((tex_res->mip_base) >> 8));
706 E32(ib, sq_tex_resource_word4);
707 E32(ib, sq_tex_resource_word5);
708 E32(ib, sq_tex_resource_word6);
715 r600_set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s)
758 PACK0(ib, SQ_TEX_SAMPLER_WORD + s->id * SQ_TEX_SAMPLER_WORD_offset, 3);
759 E32(ib, sq_tex_sampler_word0);
760 E32(ib, sq_tex_sampler_word1);
761 E32(ib, sq_tex_sampler_word2);
767 r600_set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
772 PACK0(ib, PA_SC_SCREEN_SCISSOR_TL, 2);
773 E32(ib, ((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) |
775 E32(ib, ((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) |
781 r600_set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2)
786 PACK0(ib, PA_SC_VPORT_SCISSOR_0_TL + id * PA_SC_VPORT_SCISSOR_0_TL_offset, 2);
787 E32(ib, ((x1 << PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift) |
790 E32(ib, ((x2 << PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift) |
796 r600_set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
801 PACK0(ib, PA_SC_GENERIC_SCISSOR_TL, 2);
802 E32(ib, ((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) |
805 E32(ib, ((x2 << PA_SC_GENERIC_SCISSOR_BR__BR_X_shift) |
811 r600_set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2)
816 PACK0(ib, PA_SC_WINDOW_SCISSOR_TL, 2);
817 E32(ib, ((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) |
820 E32(ib, ((x2 << PA_SC_WINDOW_SCISSOR_BR__BR_X_shift) |
826 r600_set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2)
831 PACK0(ib, PA_SC_CLIPRECT_0_TL + id * PA_SC_CLIPRECT_0_TL_offset, 2);
832 E32(ib, ((x1 << PA_SC_CLIPRECT_0_TL__TL_X_shift) |
834 E32(ib, ((x2 << PA_SC_CLIPRECT_0_BR__BR_X_shift) |
844 r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
861 r600_start_3d(pScrn, accel_state->ib);
985 r600_sq_setup(pScrn, ib, &sq_conf);
989 EREG(ib, DB_DEPTH_INFO, 0);
995 EREG(ib, TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) |
997 EREG(ib, VC_ENHANCE, 0);
998 EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
999 EREG(ib, DB_DEBUG, 0x82000000); /* ? */
1000 EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) |
1007 EREG(ib, TA_CNTL_AUX, (( 2 << GRADIENT_CREDIT_shift) |
1009 EREG(ib, VC_ENHANCE, 0);
1010 EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit);
1011 EREG(ib, DB_DEBUG, 0);
1012 EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) |
1020 PACK0(ib, SQ_VTX_BASE_VTX_LOC, 2);
1021 E32(ib, 0);
1022 E32(ib, 0);
1024 PACK0(ib, SQ_ESGS_RING_ITEMSIZE, 9);
1025 E32(ib, 0); // SQ_ESGS_RING_ITEMSIZE
1026 E32(ib, 0); // SQ_GSVS_RING_ITEMSIZE
1027 E32(ib, 0); // SQ_ESTMP_RING_ITEMSIZE
1028 E32(ib, 0); // SQ_GSTMP_RING_ITEMSIZE
1029 E32(ib, 0); // SQ_VSTMP_RING_ITEMSIZE
1030 E32(ib, 0); // SQ_PSTMP_RING_ITEMSIZE
1031 E32(ib, 0); // SQ_FBUF_RING_ITEMSIZE
1032 E32(ib, 0); // SQ_REDUC_RING_ITEMSIZE
1033 E32(ib, 0); // SQ_GS_VERT_ITEMSIZE
1036 EREG(ib, DB_DEPTH_CONTROL, 0);
1037 PACK0(ib, DB_RENDER_CONTROL, 2);
1038 E32(ib, STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit);
1040 E32(ib, FORCE_SHADER_Z_ORDER_bit);
1042 E32(ib, 0);
1043 EREG(ib, DB_ALPHA_TO_MASK, ((2 << ALPHA_TO_MASK_OFFSET0_shift) |
1047 EREG(ib, DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */
1050 PACK0(ib, DB_STENCIL_CLEAR, 2);
1051 E32(ib, 0); // DB_STENCIL_CLEAR
1052 E32(ib, 0); // DB_DEPTH_CLEAR
1054 PACK0(ib, DB_STENCILREFMASK, 3);
1055 E32(ib, 0); // DB_STENCILREFMASK
1056 E32(ib, 0); // DB_STENCILREFMASK_BF
1057 E32(ib, 0); // SX_ALPHA_REF
1059 PACK0(ib, CB_CLRCMP_CONTROL, 4);
1060 E32(ib, 1 << CLRCMP_FCN_SEL_shift); // CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC
1061 E32(ib, 0); // CB_CLRCMP_SRC
1062 E32(ib, 0); // CB_CLRCMP_DST
1063 E32(ib, 0); // CB_CLRCMP_MSK
1065 EREG(ib, CB_SHADER_MASK, OUTPUT0_ENABLE_mask);
1066 EREG(ib, R7xx_CB_SHADER_CONTROL, (RT0_ENABLE_bit));
1068 PACK0(ib, SX_ALPHA_TEST_CONTROL, 5);
1069 E32(ib, 0); // SX_ALPHA_TEST_CONTROL
1070 E32(ib, 0x00000000); // CB_BLEND_RED
1071 E32(ib, 0x00000000); // CB_BLEND_GREEN
1072 E32(ib, 0x00000000); // CB_BLEND_BLUE
1073 E32(ib, 0x00000000); // CB_BLEND_ALPHA
1075 EREG(ib, PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) |
1079 EREG(ib, R7xx_PA_SC_EDGERULE, 0x00000000);
1081 EREG(ib, R7xx_PA_SC_EDGERULE, 0xAAAAAAAA);
1083 EREG(ib, PA_SC_CLIPRECT_RULE, CLIP_RULE_mask);
1089 r600_set_clip_rect(pScrn, ib, i, 0, 0, 8192, 8192);
1092 r600_set_vport_scissor(pScrn, ib, i, 0, 0, 8192, 8192);
1095 PACK0(ib, PA_SC_MPASS_PS_CNTL, 2);
1096 E32(ib, 0);
1098 E32(ib, (WALK_ORDER_ENABLE_bit | FORCE_EOV_CNTDWN_ENABLE_bit));
1100 E32(ib, (FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit |
1103 PACK0(ib, PA_SC_LINE_CNTL, 9);
1104 E32(ib, 0); // PA_SC_LINE_CNTL
1105 E32(ib, 0); // PA_SC_AA_CONFIG
1106 E32(ib, ((2 << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit | // PA_SU_VTX_CNTL
1108 EFLOAT(ib, 1.0); // PA_CL_GB_VERT_CLIP_ADJ
1109 EFLOAT(ib, 1.0); // PA_CL_GB_VERT_DISC_ADJ
1110 EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_CLIP_ADJ
1111 EFLOAT(ib, 1.0); // PA_CL_GB_HORZ_DISC_ADJ
1112 E32(ib, 0); // PA_SC_AA_SAMPLE_LOCS_MCTX
1113 E32(ib, 0); // PA_SC_AA_SAMPLE_LOCS_8S_WD1_M
1115 EREG(ib, PA_SC_AA_MASK, 0xFFFFFFFF);
1117 PACK0(ib, PA_CL_CLIP_CNTL, 5);
1118 E32(ib, CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL
1119 E32(ib, FACE_bit); // PA_SU_SC_MODE_CNTL
1120 E32(ib, VTX_XY_FMT_bit); // PA_CL_VTE_CNTL
1121 E32(ib, 0); // PA_CL_VS_OUT_CNTL
1122 E32(ib, 0); // PA_CL_NANINF_CNTL
1124 PACK0(ib, PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
1125 E32(ib, 0); // PA_SU_POLY_OFFSET_DB_FMT_CNTL
1126 E32(ib, 0); // PA_SU_POLY_OFFSET_CLAMP
1127 E32(ib, 0); // PA_SU_POLY_OFFSET_FRONT_SCALE
1128 E32(ib, 0); // PA_SU_POLY_OFFSET_FRONT_OFFSET
1129 E32(ib, 0); // PA_SU_POLY_OFFSET_BACK_SCALE
1130 E32(ib, 0); // PA_SU_POLY_OFFSET_BACK_OFFSET
1134 EREG(ib, R7xx_SPI_THREAD_GROUPING, 0);
1136 EREG(ib, R7xx_SPI_THREAD_GROUPING, (1 << PS_GROUPING_shift));
1139 EREG(ib, SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
1141 PACK0(ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
1143 E32(ib, ((0 << SEMANTIC_shift) |
1147 E32(ib, ((1 << SEMANTIC_shift) |
1151 PACK0(ib, SPI_INPUT_Z, 4);
1152 E32(ib, 0); // SPI_INPUT_Z
1153 E32(ib, 0); // SPI_FOG_CNTL
1154 E32(ib, 0); // SPI_FOG_FUNC_SCALE
1155 E32(ib, 0); // SPI_FOG_FUNC_BIAS
1161 r600_fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
1165 PACK0(ib, VGT_MAX_VTX_INDX, 4);
1166 E32(ib, 0xffffff); // VGT_MAX_VTX_INDX
1167 E32(ib, 0); // VGT_MIN_VTX_INDX
1168 E32(ib, 0); // VGT_INDX_OFFSET
1169 E32(ib, 0); // VGT_MULTI_PRIM_IB_RESET_INDX
1171 EREG(ib, VGT_PRIMITIVEID_EN, 0);
1172 EREG(ib, VGT_MULTI_PRIM_IB_RESET_EN, 0);
1174 PACK0(ib, VGT_INSTANCE_STEP_RATE_0, 2);
1175 E32(ib, 0); // VGT_INSTANCE_STEP_RATE_0
1176 E32(ib, 0); // VGT_INSTANCE_STEP_RATE_1
1178 PACK0(ib, PA_SU_POINT_SIZE, 17);
1179 E32(ib, 0); // PA_SU_POINT_SIZE
1180 E32(ib, 0); // PA_SU_POINT_MINMAX
1181 E32(ib, (8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
1182 E32(ib, 0); // PA_SC_LINE_STIPPLE
1183 E32(ib, 0); // VGT_OUTPUT_PATH_CNTL
1184 E32(ib, 0); // VGT_HOS_CNTL
1185 E32(ib, 0); // VGT_HOS_MAX_TESS_LEVEL
1186 E32(ib, 0); // VGT_HOS_MIN_TESS_LEVEL
1187 E32(ib, 0); // VGT_HOS_REUSE_DEPTH
1188 E32(ib, 0); // VGT_GROUP_PRIM_TYPE
1189 E32(ib, 0); // VGT_GROUP_FIRST_DECR
1190 E32(ib, 0); // VGT_GROUP_DECR
1191 E32(ib, 0); // VGT_GROUP_VECT_0_CNTL
1192 E32(ib, 0); // VGT_GROUP_VECT_1_CNTL
1193 E32(ib, 0); // VGT_GROUP_VECT_0_FMT_CNTL
1194 E32(ib, 0); // VGT_GROUP_VECT_1_FMT_CNTL
1195 E32(ib, 0); // VGT_GS_MODE
1197 PACK0(ib, VGT_STRMOUT_EN, 3);
1198 E32(ib, 0); // VGT_STRMOUT_EN
1199 E32(ib, 0); // VGT_REUSE_OFF
1200 E32(ib, 0); // VGT_VTX_CNT_EN
1202 EREG(ib, VGT_STRMOUT_BUFFER_EN, 0);
1203 EREG(ib, SX_MISC, 0);
1213 r600_draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices)
1226 EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
1227 PACK3(ib, IT_INDEX_TYPE, 1);
1229 E32(ib, IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type);
1231 E32(ib, draw_conf->index_type);
1233 PACK3(ib, IT_NUM_INSTANCES, 1);
1234 E32(ib, draw_conf->num_instances);
1236 PACK3(ib, IT_DRAW_INDEX_IMMD, count);
1237 E32(ib, draw_conf->num_indices);
1238 E32(ib, draw_conf->vgt_draw_initiator);
1243 E32(ib, indices[i]);
1245 E32(ib, (indices[i] | (indices[i + 1] << 16)));
1249 E32(ib, indices[i]);
1255 r600_draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf)
1260 EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
1261 PACK3(ib, IT_INDEX_TYPE, 1);
1263 E32(ib, IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type);
1265 E32(ib, draw_conf->index_type);
1267 PACK3(ib, IT_NUM_INSTANCES, 1);
1268 E32(ib, draw_conf->num_instances);
1269 PACK3(ib, IT_DRAW_INDEX_AUTO, 2);
1270 E32(ib, draw_conf->num_indices);
1271 E32(ib, draw_conf->vgt_draw_initiator);
1289 R600IBDiscard(pScrn, accel_state->ib);
1304 r600_set_vtx_resource(pScrn, accel_state->ib, &vtx_res, RADEON_GEM_DOMAIN_GTT);
1313 r600_draw_auto(pScrn, accel_state->ib, &draw_conf);
1316 r600_wait_3d_idle_clean(pScrn, accel_state->ib);
1319 r600_cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit),
1329 R600CPFlushIndirect(pScrn, accel_state->ib);