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Lines Matching refs:accel_state

93     info->accel_state->vbo.vb_offset = 0;
94     info->accel_state->vbo.vb_start_op = -1;
574     struct radeon_accel_state *accel_state = info->accel_state;
598 				 accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr,
603 				 accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr,
851     struct radeon_accel_state *accel_state = info->accel_state;
853     if (accel_state->XInited3D)
859     accel_state->XInited3D = TRUE;
861     r600_start_3d(pScrn, accel_state->ib);
990     RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
1160     fs_conf.bo = accel_state->shaders_bo;
1278     struct radeon_accel_state *accel_state = info->accel_state;
1282     if (accel_state->vbo.vb_start_op == -1)
1288     if (accel_state->vbo.vb_offset == accel_state->vbo.vb_start_op) {
1289         R600IBDiscard(pScrn, accel_state->ib);
1294     accel_state->vbo.vb_size = accel_state->vbo.vb_offset - accel_state->vbo.vb_start_op;
1297     vtx_res.vtx_num_entries = accel_state->vbo.vb_size / 4;
1299     vtx_res.vb_addr         = accel_state->vbo.vb_mc_addr + accel_state->vbo.vb_start_op;
1300     vtx_res.bo              = accel_state->vbo.vb_bo;
1304     r600_set_vtx_resource(pScrn, accel_state->ib, &vtx_res, RADEON_GEM_DOMAIN_GTT);
1313     r600_draw_auto(pScrn, accel_state->ib, &draw_conf);
1316     r600_wait_3d_idle_clean(pScrn, accel_state->ib);
1319     r600_cp_set_surface_sync(pScrn, accel_state->ib, (CB_ACTION_ENA_bit | CB0_DEST_BASE_ENA_bit),
1320 			     accel_state->dst_size, accel_state->dst_obj.offset,
1321 			     accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain);
1323     accel_state->vbo.vb_start_op = -1;
1324     accel_state->ib_reset_op = 0;
1329 	R600CPFlushIndirect(pScrn, accel_state->ib);