Lines Matching refs:tmp0
575 int offset, i, entry, tmp, tmp0, tmp1;
797 tmp0 = RADEON_BIOS16(tmp + 0x15);
798 if (tmp0) {
799 tmp1 = RADEON_BIOS8(tmp0+2) & 0x07;
820 info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
821 info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07);
822 info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
823 info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07);
824 info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
825 info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07);
826 info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
827 info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07);
831 info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
832 info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07);
833 info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
834 info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07);
835 info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
836 info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07);
837 info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
838 info->BiosConnector[4].ddc_i2c.get_data_mask = RADEON_BIOS32(tmp0 + 0x07);
1128 int tmp0;
1163 tmp0 = RADEON_BIOS16(tmp+64+i*2);
1164 if (tmp0 == 0) break;
1165 if ((RADEON_BIOS16(tmp0) == native_mode->PanelXRes) &&
1166 (RADEON_BIOS16(tmp0+2) == native_mode->PanelYRes)) {
1167 native_mode->HBlank = (RADEON_BIOS16(tmp0+17) -
1168 RADEON_BIOS16(tmp0+19)) * 8;
1169 native_mode->HOverPlus = (RADEON_BIOS16(tmp0+21) -
1170 RADEON_BIOS16(tmp0+19) - 1) * 8;
1171 native_mode->HSyncWidth = RADEON_BIOS8(tmp0+23) * 8;
1172 native_mode->VBlank = (RADEON_BIOS16(tmp0+24) -
1173 RADEON_BIOS16(tmp0+26));
1174 native_mode->VOverPlus = ((RADEON_BIOS16(tmp0+28) & 0x7ff) -
1175 RADEON_BIOS16(tmp0+26));
1176 native_mode->VSyncWidth = ((RADEON_BIOS16(tmp0+28) & 0xf800) >> 11);
1177 native_mode->DotClock = RADEON_BIOS16(tmp0+9) * 10;