Lines Matching defs:pll
1010 RADEONPLLPtr pll = &info->pll;
1202 pll->reference_div = ref_div;
1203 pll->xclk = xclk;
1204 pll->reference_freq = xtal;
1215 RADEONPLLPtr pll = &info->pll;
1219 if (pll->reference_div < 2) {
1231 pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
1233 pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
1236 if (pll->reference_div < 2) pll->reference_div = 12;
1244 pll->pll_in_min = 100;
1245 pll->pll_in_max = 1350;
1246 pll->pll_out_min = 20000;
1247 pll->pll_out_max = 50000;
1249 pll->pll_in_min = 40;
1250 pll->pll_in_max = 500;
1251 pll->pll_out_min = 12500;
1252 pll->pll_out_max = 35000;
1257 pll->reference_freq = 1432;
1259 pll->reference_freq = 2700;
1261 pll->reference_div = 12;
1262 pll->xclk = 10300;
1271 pll->min_post_div = 2;
1272 pll->max_post_div = 0x7f;
1273 pll->min_frac_feedback_div = 0;
1274 pll->max_frac_feedback_div = 9;
1276 pll->min_post_div = 1;
1277 pll->max_post_div = 12; //16 on crtc0
1278 pll->min_frac_feedback_div = 0;
1279 pll->max_frac_feedback_div = 0;
1281 pll->min_ref_div = 2;
1282 pll->max_ref_div = 0x3ff;
1283 pll->min_feedback_div = 4;
1284 pll->max_feedback_div = 0x7ff;
1285 pll->best_vco = 0;
1289 pll->reference_freq,
1290 pll->reference_div,
1291 (unsigned)pll->pll_out_min, (unsigned)pll->pll_out_max,
1292 pll->xclk);
1300 if (min_dotclock < 12 || min_dotclock*100 >= pll->pll_out_max) {
1309 min_dotclock, ((double)pll->pll_out_min/1000));
1310 pll->pll_out_min = min_dotclock * 1000;
4783 state->pll[0][ri++] = INREG(i);
4785 state->pll[0][ri++] = INREG(i);
4789 state->pll[1][ri++] = INREG(i);
4791 state->pll[1][ri++] = INREG(i);
4817 OUTREG(i, state->pll[0][ri++]);
4819 OUTREG(i, state->pll[0][ri++]);
4823 OUTREG(i, state->pll[1][ri++]);
4825 OUTREG(i, state->pll[1][ri++]);
4927 state->pll[0].ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
4928 state->pll[0].ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV);
4929 state->pll[0].fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV);
4930 state->pll[0].post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC);
4931 state->pll[0].post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV);
4932 state->pll[0].ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL);
4933 state->pll[0].pll_cntl = INREG(AVIVO_P1PLL_CNTL);
4934 state->pll[0].int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL);
4936 state->pll[1].ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
4937 state->pll[1].ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV);
4938 state->pll[1].fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV);
4939 state->pll[1].post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC);
4940 state->pll[1].post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV);
4941 state->pll[1].ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL);
4942 state->pll[1].pll_cntl = INREG(AVIVO_P2PLL_CNTL);
4943 state->pll[1].int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL);
5340 OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll[0].ref_div_src);
5341 OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll[0].ref_div);
5342 OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll[0].fb_div);
5343 OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll[0].post_div_src);
5344 OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll[0].post_div);
5345 OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll[0].ext_ppll_cntl);
5346 OUTREG(AVIVO_P1PLL_CNTL, state->pll[0].pll_cntl);
5347 OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll[0].int_ss_cntl);
5349 OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll[1].ref_div_src);
5350 OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll[1].ref_div);
5351 OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll[1].fb_div);
5352 OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll[1].post_div_src);
5353 OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll[1].post_div);
5354 OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll[1].ext_ppll_cntl);
5355 OUTREG(AVIVO_P2PLL_CNTL, state->pll[1].pll_cntl);
5356 OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll[1].int_ss_cntl);