Lines Matching refs:INREG
290 SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL);
291 SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE);
292 SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG);
326 CardTmp = INREG(RADEON_MEM_CNTL);
336 CardTmp = INREG(RADEON_CONFIG_MEMSIZE);
345 CardTmp = INREG(RADEON_MPP_TB_CONFIG);
582 (void)INREG(RADEON_CLOCK_CNTL_DATA);
583 (void)INREG(RADEON_CRTC_GEN_CNTL);
606 save = INREG(RADEON_CLOCK_CNTL_INDEX);
609 tmp = INREG(RADEON_CLOCK_CNTL_DATA);
623 data = INREG(RADEON_CLOCK_CNTL_DATA);
652 data = INREG(RS690_MC_DATA);
655 data = INREG(RS600_MC_DATA);
659 data = INREG(RS780_MC_DATA);
664 (void)INREG(AVIVO_MC_INDEX);
665 data = INREG(AVIVO_MC_DATA);
668 (void)INREG(AVIVO_MC_INDEX);
671 (void)INREG(R300_MC_IND_INDEX);
672 data = INREG(R300_MC_IND_DATA);
675 (void)INREG(R300_MC_IND_INDEX);
707 (void)INREG(AVIVO_MC_INDEX);
710 (void)INREG(AVIVO_MC_INDEX);
714 (void)INREG(R300_MC_IND_INDEX);
717 (void)INREG(R300_MC_IND_INDEX);
729 data = INREG(RADEON_PCIE_DATA);
752 data = INREG(R600_PCIE_PORT_DATA);
773 if (INREG(R600_SRBM_STATUS) & 0x1f00)
778 if (INREG(R600_SRBM_STATUS) & 0x3f00)
805 if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE)
810 if (INREG(RADEON_MC_STATUS) & R300_MC_IDLE)
815 if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE)
883 *fb_loc = INREG(R700_MC_VM_FB_LOCATION);
885 *agp_loc = INREG(R700_MC_VM_AGP_BOT);
886 *agp_loc_hi = INREG(R700_MC_VM_AGP_TOP);
890 *fb_loc = INREG(R600_MC_VM_FB_LOCATION);
892 *agp_loc = INREG(R600_MC_VM_AGP_BOT);
893 *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
926 *fb_loc = INREG(RADEON_MC_FB_LOCATION);
928 *agp_loc = INREG(RADEON_MC_AGP_LOCATION);
940 return INREG(RADEON_PALETTE_DATA);
952 crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
962 while (!(INREG(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_SAVE) &&
975 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
985 while (!(INREG(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_SAVE) &&
1029 f1 = INREG(RADEON_CRTC_CRNT_FRAME);
1031 f2 = INREG(RADEON_CRTC_CRNT_FRAME);
1042 f3 = INREG(RADEON_CRTC_CRNT_FRAME);
1058 hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x3ff) + 1) * 8;
1059 vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0xfff) + 1);
1435 mem_size = INREG(R600_CONFIG_MEMSIZE);
1437 aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024 * 1024;
1441 mem_size = INREG(R600_CONFIG_MEMSIZE) * 1024 * 1024;
1442 aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024 * 1024;
1444 mem_size = INREG(R600_CONFIG_MEMSIZE);
1445 aper_size = INREG(R600_CONFIG_APER_SIZE);
1447 mem_size = INREG(RADEON_CONFIG_MEMSIZE);
1448 aper_size = INREG(RADEON_CONFIG_APER_SIZE);
1488 info->mc_fb_location = INREG(RADEON_NB_TOM);
1501 aper0_base = INREG(R600_CONFIG_F0_BASE);
1503 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
1565 else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1574 tmp = INREG(R600_RAMCFG);
1617 tmp = INREG(RADEON_MEM_CNTL);
1628 tmp = INREG(RADEON_MEM_CNTL);
1639 tmp = INREG(RADEON_MEM_CNTL);
1668 aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024;
1670 aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024;
1672 aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024;
1729 if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1745 uint32_t tom = INREG(RADEON_NB_TOM);
1754 pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
1758 pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) * 1024;
1760 pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
1763 pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
1790 info->MemCntl = INREG(RADEON_SDRAM_MODE_REG);
1791 info->BusCntl = INREG(RADEON_BUS_CNTL);
1987 (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK)
2320 fp2_gen_ctl_save = INREG(RADEON_FP2_GEN_CNTL);
3969 OUTREG(AVIVO_VGA_RENDER_CONTROL, INREG(AVIVO_VGA_RENDER_CONTROL) & ~AVIVO_VGA_VSTATUS_CNTL_MASK);
3970 OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
3971 OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
3972 OUTREG(EVERGREEN_D3VGA_CONTROL, INREG(EVERGREEN_D3VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
3973 OUTREG(EVERGREEN_D4VGA_CONTROL, INREG(EVERGREEN_D4VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
3974 OUTREG(EVERGREEN_D5VGA_CONTROL, INREG(EVERGREEN_D5VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
3975 OUTREG(EVERGREEN_D6VGA_CONTROL, INREG(EVERGREEN_D6VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
3978 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
3980 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
3982 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
3984 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
3987 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
3989 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
3991 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
3993 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
3995 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
3997 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
3999 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
4001 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
4038 OUTREG(AVIVO_VGA_RENDER_CONTROL, INREG(AVIVO_VGA_RENDER_CONTROL) &~ AVIVO_VGA_VSTATUS_CNTL_MASK);
4040 OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
4041 OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
4044 tmp = INREG(AVIVO_D1CRTC_CONTROL);
4047 tmp = INREG(AVIVO_D2CRTC_CONTROL);
4050 tmp = INREG(AVIVO_D2CRTC_CONTROL);
4108 old_mc_status = INREG(RADEON_MC_STATUS);
4111 ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
4113 crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
4115 crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
4123 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
4140 (unsigned int)INREG(RADEON_MC_STATUS), (unsigned int)old_mc_status);
4164 (void)INREG(RADEON_MC_FB_LOCATION);
4180 while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) {
4193 while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) {
4211 (void)INREG(RADEON_OV0_BASE_ADDR);
4306 save->surfaces[surfnr][0] = INREG(RADEON_SURFACE0_INFO + 16 * surfnr);
4307 save->surfaces[surfnr][1] = INREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr);
4308 save->surfaces[surfnr][2] = INREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr);
4477 save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR);
4478 save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR);
4479 save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR);
4494 save->palette[palID][i] = INREG(RADEON_PALETTE_30_DATA);
4529 state->grph.enable = INREG(offset + EVERGREEN_GRPH_ENABLE);
4530 state->grph.control = INREG(offset + EVERGREEN_GRPH_CONTROL);
4531 state->grph.swap_control = INREG(offset + EVERGREEN_GRPH_SWAP_CONTROL);
4532 state->grph.prim_surf_addr = INREG(offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS);
4533 state->grph.sec_surf_addr = INREG(offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS);
4534 state->grph.pitch = INREG(offset + EVERGREEN_GRPH_PITCH);
4535 state->grph.prim_surf_addr_hi = INREG(offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH);
4536 state->grph.sec_surf_addr_hi = INREG(offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH);
4537 state->grph.x_offset = INREG(offset + EVERGREEN_GRPH_SURFACE_OFFSET_X);
4538 state->grph.y_offset = INREG(offset + EVERGREEN_GRPH_SURFACE_OFFSET_Y);
4539 state->grph.x_start = INREG(offset + EVERGREEN_GRPH_X_START);
4540 state->grph.y_start = INREG(offset + EVERGREEN_GRPH_Y_START);
4541 state->grph.x_end = INREG(offset + EVERGREEN_GRPH_X_END);
4542 state->grph.y_end = INREG(offset + EVERGREEN_GRPH_Y_END);
4544 state->grph.desktop_height = INREG(offset + EVERGREEN_DESKTOP_HEIGHT);
4545 state->grph.viewport_start = INREG(offset + EVERGREEN_VIEWPORT_START);
4546 state->grph.viewport_size = INREG(offset + EVERGREEN_VIEWPORT_SIZE);
4547 state->grph.mode_data_format = INREG(offset + EVERGREEN_DATA_FORMAT);
4609 state->crtc[i] = INREG(offset + dce4_crtc_regs[i]);
4633 state->scl[i] = INREG(offset + dce4_scl_regs[i]);
4658 state->fmt[index++] = INREG(offset + i);
4683 state->dig[i] = INREG(offset + dce4_dig_regs[i]);
4727 state->uniphy[index][ri++] = INREG(0x6600 + uniphy_offset[index] + i);
4747 state->dig[ri++] = INREG(i);
4749 state->dig[ri++] = INREG(i);
4771 state->vga_pll[0][ri++] = INREG(i);
4775 state->vga_pll[1][ri++] = INREG(i);
4779 state->vga_pll[2][ri++] = INREG(i);
4783 state->pll[0][ri++] = INREG(i);
4785 state->pll[0][ri++] = INREG(i);
4789 state->pll[1][ri++] = INREG(i);
4791 state->pll[1][ri++] = INREG(i);
4795 state->pll_route[ri++] = INREG(i);
4846 state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL);
4847 state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL);
4848 state->vga3_cntl = INREG(EVERGREEN_D3VGA_CONTROL);
4849 state->vga4_cntl = INREG(EVERGREEN_D4VGA_CONTROL);
4850 state->vga5_cntl = INREG(EVERGREEN_D5VGA_CONTROL);
4851 state->vga6_cntl = INREG(EVERGREEN_D6VGA_CONTROL);
4852 state->vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL);
4866 state->dac[i][j] = INREG(dce4_dac_regs[j] + offset);
4917 // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE);
4918 // state->vga_fb_start = INREG(AVIVO_VGA_FB_START);
4919 state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL);
4920 state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL);
4921 state->vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL);
4923 state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN);
4924 state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL);
4925 state->dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT);
4927 state->pll[0].ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
4928 state->pll[0].ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV);
4929 state->pll[0].fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV);
4930 state->pll[0].post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC);
4931 state->pll[0].post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV);
4932 state->pll[0].ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL);
4933 state->pll[0].pll_cntl = INREG(AVIVO_P1PLL_CNTL);
4934 state->pll[0].int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL);
4936 state->pll[1].ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
4937 state->pll[1].ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV);
4938 state->pll[1].fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV);
4939 state->pll[1].post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC);
4940 state->pll[1].post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV);
4941 state->pll[1].ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL);
4942 state->pll[1].pll_cntl = INREG(AVIVO_P2PLL_CNTL);
4943 state->pll[1].int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL);
4945 state->vga25_ppll.ref_div_src = INREG(AVIVO_VGA25_PPLL_REF_DIV_SRC);
4946 state->vga25_ppll.ref_div = INREG(AVIVO_VGA25_PPLL_REF_DIV);
4947 state->vga25_ppll.fb_div = INREG(AVIVO_VGA25_PPLL_FB_DIV);
4948 state->vga25_ppll.post_div_src = INREG(AVIVO_VGA25_PPLL_POST_DIV_SRC);
4949 state->vga25_ppll.post_div = INREG(AVIVO_VGA25_PPLL_POST_DIV);
4950 state->vga25_ppll.pll_cntl = INREG(AVIVO_VGA25_PPLL_CNTL);
4952 state->vga28_ppll.ref_div_src = INREG(AVIVO_VGA28_PPLL_REF_DIV_SRC);
4953 state->vga28_ppll.ref_div = INREG(AVIVO_VGA28_PPLL_REF_DIV);
4954 state->vga28_ppll.fb_div = INREG(AVIVO_VGA28_PPLL_FB_DIV);
4955 state->vga28_ppll.post_div_src = INREG(AVIVO_VGA28_PPLL_POST_DIV_SRC);
4956 state->vga28_ppll.post_div = INREG(AVIVO_VGA28_PPLL_POST_DIV);
4957 state->vga28_ppll.pll_cntl = INREG(AVIVO_VGA28_PPLL_CNTL);
4959 state->vga41_ppll.ref_div_src = INREG(AVIVO_VGA41_PPLL_REF_DIV_SRC);
4960 state->vga41_ppll.ref_div = INREG(AVIVO_VGA41_PPLL_REF_DIV);
4961 state->vga41_ppll.fb_div = INREG(AVIVO_VGA41_PPLL_FB_DIV);
4962 state->vga41_ppll.post_div_src = INREG(AVIVO_VGA41_PPLL_POST_DIV_SRC);
4963 state->vga41_ppll.post_div = INREG(AVIVO_VGA41_PPLL_POST_DIV);
4964 state->vga41_ppll.pll_cntl = INREG(AVIVO_VGA41_PPLL_CNTL);
4966 state->crtc[0].pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL);
4968 state->crtc[0].h_total = INREG(AVIVO_D1CRTC_H_TOTAL);
4969 state->crtc[0].h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END);
4970 state->crtc[0].h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A);
4971 state->crtc[0].h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL);
4972 state->crtc[0].h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B);
4973 state->crtc[0].h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL);
4975 state->crtc[0].v_total = INREG(AVIVO_D1CRTC_V_TOTAL);
4976 state->crtc[0].v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END);
4977 state->crtc[0].v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A);
4978 state->crtc[0].v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL);
4979 state->crtc[0].v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B);
4980 state->crtc[0].v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL);
4982 state->crtc[0].control = INREG(AVIVO_D1CRTC_CONTROL);
4983 state->crtc[0].blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL);
4984 state->crtc[0].interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL);
4985 state->crtc[0].stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL);
4987 state->crtc[0].cursor_control = INREG(AVIVO_D1CUR_CONTROL);
4989 state->grph[0].enable = INREG(AVIVO_D1GRPH_ENABLE);
4990 state->grph[0].control = INREG(AVIVO_D1GRPH_CONTROL);
4991 state->grph[0].control = INREG(AVIVO_D1GRPH_CONTROL);
4992 state->grph[0].prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS);
4993 state->grph[0].sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS);
4994 state->grph[0].pitch = INREG(AVIVO_D1GRPH_PITCH);
4995 state->grph[0].x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X);
4996 state->grph[0].y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y);
4997 state->grph[0].x_start = INREG(AVIVO_D1GRPH_X_START);
4998 state->grph[0].y_start = INREG(AVIVO_D1GRPH_Y_START);
4999 state->grph[0].x_end = INREG(AVIVO_D1GRPH_X_END);
5000 state->grph[0].y_end = INREG(AVIVO_D1GRPH_Y_END);
5002 state->grph[0].desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT);
5003 state->grph[0].viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START);
5004 state->grph[0].viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE);
5005 state->grph[0].mode_data_format = INREG(AVIVO_D1MODE_DATA_FORMAT);
5007 state->crtc[1].pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL);
5009 state->crtc[1].h_total = INREG(AVIVO_D2CRTC_H_TOTAL);
5010 state->crtc[1].h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END);
5011 state->crtc[1].h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A);
5012 state->crtc[1].h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL);
5013 state->crtc[1].h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B);
5014 state->crtc[1].h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL);
5016 state->crtc[1].v_total = INREG(AVIVO_D2CRTC_V_TOTAL);
5017 state->crtc[1].v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END);
5018 state->crtc[1].v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A);
5019 state->crtc[1].v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL);
5020 state->crtc[1].v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B);
5021 state->crtc[1].v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL);
5023 state->crtc[1].control = INREG(AVIVO_D2CRTC_CONTROL);
5024 state->crtc[1].blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL);
5025 state->crtc[1].interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL);
5026 state->crtc[1].stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL);
5028 state->crtc[1].cursor_control = INREG(AVIVO_D2CUR_CONTROL);
5030 state->grph[1].enable = INREG(AVIVO_D2GRPH_ENABLE);
5031 state->grph[1].control = INREG(AVIVO_D2GRPH_CONTROL);
5032 state->grph[1].control = INREG(AVIVO_D2GRPH_CONTROL);
5033 state->grph[1].prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS);
5034 state->grph[1].sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS);
5035 state->grph[1].pitch = INREG(AVIVO_D2GRPH_PITCH);
5036 state->grph[1].x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X);
5037 state->grph[1].y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y);
5038 state->grph[1].x_start = INREG(AVIVO_D2GRPH_X_START);
5039 state->grph[1].y_start = INREG(AVIVO_D2GRPH_Y_START);
5040 state->grph[1].x_end = INREG(AVIVO_D2GRPH_X_END);
5041 state->grph[1].y_end = INREG(AVIVO_D2GRPH_Y_END);
5043 state->grph[1].desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT);
5044 state->grph[1].viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START);
5045 state->grph[1].viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE);
5046 state->grph[1].mode_data_format = INREG(AVIVO_D2MODE_DATA_FORMAT);
5050 state->dvoa[0] = INREG(0x7080);
5051 state->dvoa[1] = INREG(0x7084);
5052 state->dvoa[2] = INREG(0x708c);
5053 state->dvoa[3] = INREG(0x7090);
5054 state->dvoa[4] = INREG(0x7094);
5055 state->dvoa[5] = INREG(0x70ac);
5056 state->dvoa[6] = INREG(0x70b0);
5061 state->daca[j] = INREG(i);
5062 state->dacb[j] = INREG(i + 0x100);
5066 state->daca[j] = INREG(i);
5067 state->dacb[j] = INREG(i + 0x100);
5071 state->daca[j] = INREG(i);
5072 state->dacb[j] = INREG(i + 0x100);
5076 state->daca[j] = INREG(i);
5077 state->dacb[j] = INREG(i + 0x100);
5080 state->daca[j] = INREG(0x7050);
5081 state->dacb[j] = INREG(0x7050 + 0x100);
5086 state->fmt1[j] = INREG(i);
5087 state->fmt2[j] = INREG(i + 0x800);
5094 state->dig1[j] = INREG(i);
5095 state->dig2[j] = INREG(i + 0x400);
5099 state->dig1[j] = INREG(i);
5100 state->dig2[j] = INREG(i + 0x400);
5107 state->hdmi1[j] = INREG(i);
5108 state->hdmi2[j] = INREG(i + 0x400);
5112 state->hdmi1[j] = INREG(i);
5113 state->hdmi2[j] = INREG(i + 0x400);
5116 state->hdmi1[j] = INREG(0x7428);
5117 state->hdmi2[j] = INREG(0x7828);
5122 state->aux_cntl1[j] = INREG(i);
5123 state->aux_cntl2[j] = INREG(i + 0x040);
5124 state->aux_cntl3[j] = INREG(i + 0x400);
5125 state->aux_cntl4[j] = INREG(i + 0x440);
5127 state->aux_cntl5[j] = INREG(i + 0x500);
5128 state->aux_cntl6[j] = INREG(i + 0x540);
5137 state->uniphy1[j] = INREG(i);
5138 state->uniphy2[j] = INREG(i + 0x20);
5139 state->uniphy3[j] = INREG(i + 0x400);
5140 state->uniphy4[j] = INREG(i + 0x420);
5141 state->uniphy5[j] = INREG(i + 0x840);
5142 state->uniphy6[j] = INREG(i + 0x940);
5146 state->uniphy1[j] = INREG(i);
5147 state->uniphy2[j] = INREG(i + 0x20);
5148 state->uniphy3[j] = INREG(i + 0x400);
5149 state->uniphy4[j] = INREG(i + 0x420);
5150 state->uniphy5[j] = INREG(i + 0x840);
5151 state->uniphy6[j] = INREG(i + 0x940);
5156 state->uniphy1[j] = INREG(i);
5157 state->uniphy2[j] = INREG(i + 0x100);
5164 state->phy[j] = INREG(i);
5168 state->phy[j] = INREG(i);
5171 state->phy[j] = INREG(0x7f40);
5176 state->lvtma[j] = INREG(i);
5180 state->lvtma[j] = INREG(i);
5187 state->dvoa[j] = INREG(i);
5194 state->daca[j] = INREG(i);
5195 state->dacb[j] = INREG(i + 0x200);
5199 state->daca[j] = INREG(i);
5200 state->dacb[j] = INREG(i + 0x200);
5204 state->daca[j] = INREG(i);
5205 state->dacb[j] = INREG(i + 0x200);
5212 state->tmdsa[j] = INREG(i);
5216 state->tmdsa[j] = INREG(i);
5223 state->lvtma[j] = INREG(i);
5233 state->ddia[j] = INREG(i);
5242 state->d1scl[j] = INREG(i);
5243 state->d2scl[j] = INREG(i + 0x800);
5247 state->d1scl[j] = INREG(i);
5248 state->d2scl[j] = INREG(i + 0x800);
5253 state->dxscl[j] = INREG(i);
5256 state->dxscl[6] = INREG(0x6e30);
5257 state->dxscl[7] = INREG(0x6e34);
5283 (INREG(AVIVO_D1CRTC_CONTROL) & ~0x300) | 0x01000000);
5285 (INREG(AVIVO_D2CRTC_CONTROL) & ~0x300) | 0x01000000);
5287 INREG(AVIVO_D1CRTC_CONTROL) & ~0x1);
5289 INREG(AVIVO_D2CRTC_CONTROL) & ~0x1);
5291 INREG(AVIVO_D1CRTC_CONTROL) | 0x100);
5293 INREG(AVIVO_D2CRTC_CONTROL) | 0x100);
5547 state->phy[j] = INREG(0x7f40);
5638 INREG(AVIVO_D1CRTC_CONTROL);
5643 INREG(AVIVO_D2CRTC_CONTROL);
5724 save->bios_0_scratch = INREG(R600_BIOS_0_SCRATCH);
5725 save->bios_1_scratch = INREG(R600_BIOS_1_SCRATCH);
5726 save->bios_2_scratch = INREG(R600_BIOS_2_SCRATCH);
5727 save->bios_3_scratch = INREG(R600_BIOS_3_SCRATCH);
5728 save->bios_4_scratch = INREG(R600_BIOS_4_SCRATCH);
5729 save->bios_5_scratch = INREG(R600_BIOS_5_SCRATCH);
5730 save->bios_6_scratch = INREG(R600_BIOS_6_SCRATCH);
5731 save->bios_7_scratch = INREG(R600_BIOS_7_SCRATCH);
5733 save->bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH);
5734 save->bios_1_scratch = INREG(RADEON_BIOS_1_SCRATCH);
5735 save->bios_2_scratch = INREG(RADEON_BIOS_2_SCRATCH);
5736 save->bios_3_scratch = INREG(RADEON_BIOS_3_SCRATCH);
5737 save->bios_4_scratch = INREG(RADEON_BIOS_4_SCRATCH);
5738 save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH);
5739 save->bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH);
5740 save->bios_7_scratch = INREG(RADEON_BIOS_7_SCRATCH);
5797 save->dp_datatype = INREG(RADEON_DP_DATATYPE);
5798 save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
5799 save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
6120 crtcoffsetcntl = INREG(regcntl) & ~0xf;
6287 unsigned int sctrl = INREG(RADEON_SURFACE_CNTL);
6354 unsigned int sctrl = INREG(RADEON_SURFACE_CNTL);