Lines Matching refs:restore
323 * two channels with the two channels configured differently), restore
2317 * is enabled. Clear and restore FP2_ON around int10 to avoid this.
3756 /* restore the memory map here otherwise we may get a hang when
3790 * our local image to make sure we restore them properly on mode
3938 RADEONSavePtr restore)
3955 (unsigned)restore->mc_fb_location, (unsigned int)mc_fb_loc);
3958 (unsigned)restore->mc_agp_location);
3961 if (mc_fb_loc != restore->mc_fb_location ||
3962 mc_agp_loc != restore->mc_agp_location) {
4023 restore->mc_fb_location,
4024 restore->mc_agp_location,
4025 restore->mc_agp_location_hi);
4027 OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location & 0xffff) << 16);
4031 if (mc_fb_loc != restore->mc_fb_location ||
4032 mc_agp_loc != restore->mc_agp_location) {
4071 restore->mc_fb_location,
4072 restore->mc_agp_location,
4073 restore->mc_agp_location_hi);
4076 OUTREG(AVIVO_HDP_FB_LOCATION, restore->mc_fb_location);
4078 OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000);
4091 if (mc_fb_loc != restore->mc_fb_location ||
4092 mc_agp_loc != restore->mc_agp_location) {
4157 OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location);
4158 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, restore->mc_fb_location,
4162 restore->mc_agp_location, 0);
4207 OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr);
4209 OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr);
4210 OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr);
4284 /* restore original surface info (for fb console). */
4285 static void RADEONRestoreSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr restore)
4292 OUTREG(RADEON_SURFACE0_INFO + 16 * surfnr, restore->surfaces[surfnr][0]);
4293 OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr, restore->surfaces[surfnr][1]);
4294 OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr, restore->surfaces[surfnr][2]);
4498 static void RADEONRestorePalette(ScrnInfoPtr pScrn, RADEONSavePtr restore)
4504 if (restore->palette_saved[1]) {
4509 OUTREG(RADEON_PALETTE_30_DATA, restore->palette[1][i]);
4512 if (restore->palette_saved[0]) {
4517 OUTREG(RADEON_PALETTE_30_DATA, restore->palette[0][i]);
4872 dce4_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
4876 struct dce4_state *state = &restore->dce4;
5268 avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
5272 struct avivo_state *state = &restore->avivo;
5663 static void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore)
5667 struct avivo_state *state = &restore->avivo;
5674 static void dce4_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore)
5678 struct dce4_state *state = &restore->dce4;
5691 RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
5697 OUTREG(R600_BIOS_0_SCRATCH, restore->bios_0_scratch);
5698 OUTREG(R600_BIOS_1_SCRATCH, restore->bios_1_scratch);
5699 OUTREG(R600_BIOS_2_SCRATCH, restore->bios_2_scratch);
5700 OUTREG(R600_BIOS_3_SCRATCH, restore->bios_3_scratch);
5701 OUTREG(R600_BIOS_4_SCRATCH, restore->bios_4_scratch);
5702 OUTREG(R600_BIOS_5_SCRATCH, restore->bios_5_scratch);
5703 OUTREG(R600_BIOS_6_SCRATCH, restore->bios_6_scratch);
5704 OUTREG(R600_BIOS_7_SCRATCH, restore->bios_7_scratch);
5706 OUTREG(RADEON_BIOS_0_SCRATCH, restore->bios_0_scratch);
5707 OUTREG(RADEON_BIOS_1_SCRATCH, restore->bios_1_scratch);
5708 OUTREG(RADEON_BIOS_2_SCRATCH, restore->bios_2_scratch);
5709 OUTREG(RADEON_BIOS_3_SCRATCH, restore->bios_3_scratch);
5710 OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch);
5711 OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch);
5712 OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch);
5713 OUTREG(RADEON_BIOS_7_SCRATCH, restore->bios_7_scratch);
5758 /* Save everything needed to restore the original VC state */
5829 RADEONSavePtr restore = info->SavedReg;
5846 RADEONRestoreMemMapRegisters(pScrn, restore);
5847 dce4_restore(pScrn, restore);
5850 RADEONRestoreMemMapRegisters(pScrn, restore);
5851 avivo_restore(pScrn, restore);
5853 OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset);
5854 OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype);
5855 OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
5856 OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl);
5859 RADEONRestoreMemMapRegisters(pScrn, restore);
5860 RADEONRestoreCommonRegisters(pScrn, restore);
5862 RADEONRestorePalette(pScrn, restore);
5864 RADEONRestoreCrtc2Registers(pScrn, restore);
5865 RADEONRestorePLL2Registers(pScrn, restore);
5868 RADEONRestoreCrtcRegisters(pScrn, restore);
5869 RADEONRestorePLLRegisters(pScrn, restore);
5870 RADEONRestoreRMXRegisters(pScrn, restore);
5871 RADEONRestoreFPRegisters(pScrn, restore);
5872 RADEONRestoreFP2Registers(pScrn, restore);
5873 RADEONRestoreLVDSRegisters(pScrn, restore);
5876 RADEONRestoreTVRegisters(pScrn, restore);
5879 OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
5882 RADEONRestoreBIOSRegisters(pScrn, restore);
5896 RADEONRestoreSurfaces(pScrn, restore);
5926 /* to restore console mode, DAC registers should be set after every other registers are set,
5930 dce4_restore_vga_regs(pScrn, restore);
5932 avivo_restore_vga_regs(pScrn, restore);
5934 RADEONRestoreDACRegisters(pScrn, restore);