Lines Matching refs:ri
4725 int i, ri = 0;
4727 state->uniphy[index][ri++] = INREG(0x6600 + uniphy_offset[index] + i);
4735 int i, ri = 0;
4737 OUTREG(0x6600 + uniphy_offset[index] + i, state->uniphy[index][ri++]);
4744 int i, ri = 0;
4747 state->dig[ri++] = INREG(i);
4749 state->dig[ri++] = INREG(i);
4756 int i, ri = 0;
4759 OUTREG(i, state->dig[ri++]);
4761 OUTREG(i, state->dig[ri++]);
4768 int i, ri = 0;
4771 state->vga_pll[0][ri++] = INREG(i);
4773 ri = 0;
4775 state->vga_pll[1][ri++] = INREG(i);
4777 ri = 0;
4779 state->vga_pll[2][ri++] = INREG(i);
4781 ri = 0;
4783 state->pll[0][ri++] = INREG(i);
4785 state->pll[0][ri++] = INREG(i);
4787 ri = 0;
4789 state->pll[1][ri++] = INREG(i);
4791 state->pll[1][ri++] = INREG(i);
4793 ri = 0;
4795 state->pll_route[ri++] = INREG(i);
4802 int i, ri = 0;
4805 OUTREG(i, state->vga_pll[0][ri++]);
4807 ri = 0;
4809 OUTREG(i, state->vga_pll[1][ri++]);
4811 ri = 0;
4813 OUTREG(i, state->vga_pll[2][ri++]);
4815 ri = 0;
4817 OUTREG(i, state->pll[0][ri++]);
4819 OUTREG(i, state->pll[0][ri++]);
4821 ri = 0;
4823 OUTREG(i, state->pll[1][ri++]);
4825 OUTREG(i, state->pll[1][ri++]);
4827 ri = 0;
4829 OUTREG(i, state->pll_route[ri++]);