Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa

Lines Matching refs:state_2d
97     if (info->state_2d.op == 0 && op == 0)
100     has_src = info->state_2d.src_pitch_offset || (info->cs && info->state_2d.src_bo);
107     OUT_ACCEL_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, info->state_2d.default_sc_bottom_right);
108     OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->state_2d.dp_gui_master_cntl);
109     OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, info->state_2d.dp_brush_frgd_clr);
110     OUT_ACCEL_REG(RADEON_DP_BRUSH_BKGD_CLR, info->state_2d.dp_brush_bkgd_clr);
111     OUT_ACCEL_REG(RADEON_DP_SRC_FRGD_CLR,   info->state_2d.dp_src_frgd_clr);
112     OUT_ACCEL_REG(RADEON_DP_SRC_BKGD_CLR,   info->state_2d.dp_src_bkgd_clr);
113     OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, info->state_2d.dp_write_mask);
114     OUT_ACCEL_REG(RADEON_DP_CNTL, info->state_2d.dp_cntl);
116     OUT_ACCEL_REG(RADEON_DST_PITCH_OFFSET, info->state_2d.dst_pitch_offset);
118 	OUT_RELOC(info->state_2d.dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
121 	    OUT_ACCEL_REG(RADEON_SRC_PITCH_OFFSET, info->state_2d.src_pitch_offset);
123 		OUT_RELOC(info->state_2d.src_bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
129 	info->state_2d.op = op;
153     info->state_2d.op = 0;
191 	    info->state_2d.dst_bo = driver_priv->bo;
195     info->state_2d.default_sc_bottom_right = (RADEON_DEFAULT_SC_RIGHT_MAX |
197     info->state_2d.dp_brush_bkgd_clr = 0x00000000;
198     info->state_2d.dp_src_frgd_clr = 0xffffffff;
199     info->state_2d.dp_src_bkgd_clr = 0x00000000;
200     info->state_2d.dp_gui_master_cntl = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
206     info->state_2d.dp_brush_frgd_clr = fg;
207     info->state_2d.dp_cntl = (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM);
208     info->state_2d.dp_write_mask = pm;
209     info->state_2d.dst_pitch_offset = dst_pitch_offset;
210     info->state_2d.src_pitch_offset = 0;
211     info->state_2d.src_bo = NULL;
255     info->state_2d.dp_gui_master_cntl = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
263     info->state_2d.dp_cntl = ((info->accel_state->xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) |
265     info->state_2d.dp_brush_frgd_clr = 0xffffffff;
266     info->state_2d.dp_brush_bkgd_clr = 0x00000000;
267     info->state_2d.dp_src_frgd_clr = 0xffffffff;
268     info->state_2d.dp_src_bkgd_clr = 0x00000000;
269     info->state_2d.dp_write_mask = planemask;
270     info->state_2d.dst_pitch_offset = dst_pitch_offset;
271     info->state_2d.src_pitch_offset = src_pitch_offset;
272     info->state_2d.default_sc_bottom_right =  (RADEON_DEFAULT_SC_RIGHT_MAX
308 	info->state_2d.src_bo = driver_priv->bo;
312 	info->state_2d.dst_bo = driver_priv->bo;