Cross Reference: /xsrc/external/mit/xf86-video-ati/dist/src/radeon_exa

Lines Matching refs:accel_state
296     info->accel_state->need_src_tile_x = info->accel_state->need_src_tile_y = FALSE;
297     info->accel_state->src_tile_width = info->accel_state->src_tile_height = 65536; /* "infinite" */
310 	    info->accel_state->need_src_tile_x = (w & (w - 1)) != 0 || badPitch;
311 	    info->accel_state->need_src_tile_y = (h & (h - 1)) != 0;
313 	    if ((info->accel_state->need_src_tile_x ||
314 		 info->accel_state->need_src_tile_y) &&
319 		info->accel_state->need_src_tile_x =
320 		    info->accel_state->need_src_tile_y =
321 		    info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y;
324 	if (info->accel_state->need_src_tile_x)
325 	    info->accel_state->src_tile_width = w;
326 	if (info->accel_state->need_src_tile_y)
327 	    info->accel_state->src_tile_height = h;
402 	!(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y));
432     info->accel_state->texW[unit] = w;
433     info->accel_state->texH[unit] = h;
491 	info->accel_state->is_transform[unit] = TRUE;
492 	info->accel_state->transform[unit] = pPict->transform;
494 	info->accel_state->is_transform[unit] = FALSE;
585     info->accel_state->composite_op = op;
586     info->accel_state->dst_pic = pDstPicture;
587     info->accel_state->msk_pic = pMaskPicture;
588     info->accel_state->src_pic = pSrcPicture;
589     info->accel_state->dst_pix = pDst;
590     info->accel_state->msk_pix = pMask;
591     info->accel_state->src_pix = pSrc;
687 	info->accel_state->is_transform[1] = FALSE;
819 	!(unit == 0 && (info->accel_state->need_src_tile_x || info->accel_state->need_src_tile_y));
849     info->accel_state->texW[unit] = w;
850     info->accel_state->texH[unit] = h;
907 	info->accel_state->is_transform[unit] = TRUE;
908 	info->accel_state->transform[unit] = pPict->transform;
910 	info->accel_state->is_transform[unit] = FALSE;
1060 	info->accel_state->is_transform[1] = FALSE;
1241 	if ((unit == 0) && info->accel_state->msk_pic)
1286 	if (unit != 0 || !info->accel_state->need_src_tile_x)
1291 	if (unit != 0 || !info->accel_state->need_src_tile_y)
1340 	info->accel_state->is_transform[unit] = TRUE;
1341 	info->accel_state->transform[unit] = pPict->transform;
1344 	if (info->accel_state->has_tcl) {
1345 	    info->accel_state->texW[unit] = 1;
1346 	    info->accel_state->texH[unit] = 1;
1365 	    info->accel_state->texW[unit] = w;
1366 	    info->accel_state->texH[unit] = h;
1369 	info->accel_state->is_transform[unit] = FALSE;
1372 	if (info->accel_state->has_tcl) {
1373 	    info->accel_state->texW[unit] = 1;
1374 	    info->accel_state->texH[unit] = 1;
1394 	    info->accel_state->texW[unit] = w;
1395 	    info->accel_state->texH[unit] = h;
1568 	info->accel_state->is_transform[1] = FALSE;
1572     if (info->accel_state->has_tcl) {
1633     if (info->accel_state->has_tcl) {
2181     if (info->accel_state->draw_header) {
2183 	    info->accel_state->draw_header[0] = CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD,
2184 							   info->accel_state->num_vtx *
2185 							   info->accel_state->vtx_count + 1);
2186 	    info->accel_state->draw_header[2] = (RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
2190 						 (info->accel_state->num_vtx << RADEON_CP_VC_CNTL_NUM_SHIFT));
2192 	    info->accel_state->draw_header[0] = CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
2193 							   info->accel_state->num_vtx *
2194 							   info->accel_state->vtx_count);
2195 	    info->accel_state->draw_header[1] = (RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST |
2197 						 (info->accel_state->num_vtx << RADEON_CP_VC_CNTL_NUM_SHIFT));
2199 	    info->accel_state->draw_header[0] = CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
2200 							   info->accel_state->num_vtx *
2201 							   info->accel_state->vtx_count);
2202 	    info->accel_state->draw_header[1] = (RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
2204 						 (info->accel_state->num_vtx << RADEON_CP_VC_CNTL_NUM_SHIFT));
2206 	info->accel_state->draw_header = NULL;
2225     struct radeon_accel_state *accel_state = info->accel_state;
2229     if (!accel_state->src_pic->pDrawable)
2230 	pScreen->DestroyPixmap(accel_state->src_pix);
2232     if (accel_state->msk_pic && !accel_state->msk_pic->pDrawable)
2233 	pScreen->DestroyPixmap(accel_state->msk_pix);
2313 	FUNC_NAME(RadeonFinishComposite)(info->accel_state->dst_pix);
2318 	info->accel_state->exa->PrepareComposite(info->accel_state->composite_op,
2319 						 info->accel_state->src_pic,
2320 						 info->accel_state->msk_pic,
2321 						 info->accel_state->dst_pic,
2322 						 info->accel_state->src_pix,
2323 						 info->accel_state->msk_pix,
2324 						 info->accel_state->dst_pix);
2337     if (info->accel_state->is_transform[0]) {
2338 	if ((info->ChipFamily < CHIP_FAMILY_R300) || !info->accel_state->has_tcl) {
2339 	    transformPoint(info->accel_state->transform[0], &srcTopLeft);
2340 	    transformPoint(info->accel_state->transform[0], &srcTopRight);
2341 	    transformPoint(info->accel_state->transform[0], &srcBottomLeft);
2342 	    transformPoint(info->accel_state->transform[0], &srcBottomRight);
2346     if (info->accel_state->msk_pic) {
2356 	if (info->accel_state->is_transform[1]) {
2357 	    if ((info->ChipFamily < CHIP_FAMILY_R300) || !info->accel_state->has_tcl) {
2358 		transformPoint(info->accel_state->transform[1], &maskTopLeft);
2359 		transformPoint(info->accel_state->transform[1], &maskTopRight);
2360 		transformPoint(info->accel_state->transform[1], &maskBottomLeft);
2361 		transformPoint(info->accel_state->transform[1], &maskBottomRight);
2369     if (info->accel_state->vsync)
2376 	if (!info->accel_state->draw_header) {
2381 		info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
2384 		info->accel_state->draw_header = __head;
2385 	    info->accel_state->num_vtx = 0;
2386 	    info->accel_state->vtx_count = vtx_count;
2390 	    if (info->accel_state->msk_pic)
2405 	info->accel_state->num_vtx += 3;
2408 	if (!info->accel_state->draw_header) {
2413 		info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
2416 		info->accel_state->draw_header = __head;
2417 	    info->accel_state->num_vtx = 0;
2418 	    info->accel_state->vtx_count = vtx_count;
2428 	info->accel_state->num_vtx += 4;
2431 	if (!info->accel_state->draw_header) {
2436 		info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
2439 		info->accel_state->draw_header = __head;
2440 	    info->accel_state->num_vtx = 0;
2441 	    info->accel_state->vtx_count = vtx_count;
2451 	info->accel_state->num_vtx += 3;
2477     if (info->accel_state->msk_pic) {
2480 			 xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0],      xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0],
2481 			 xFixedToFloat(maskTopLeft.x) / info->accel_state->texW[1],     xFixedToFloat(maskTopLeft.y) / info->accel_state->texH[1]);
2484 		xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0],   xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0],
2485 		xFixedToFloat(maskBottomLeft.x) / info->accel_state->texW[1],  xFixedToFloat(maskBottomLeft.y) / info->accel_state->texH[1]);
2487 		xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0],  xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0],
2488 		xFixedToFloat(maskBottomRight.x) / info->accel_state->texW[1], xFixedToFloat(maskBottomRight.y) / info->accel_state->texH[1]);
2490 		xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0],     xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0],
2491 		xFixedToFloat(maskTopRight.x) / info->accel_state->texW[1],    xFixedToFloat(maskTopRight.y) / info->accel_state->texH[1]);
2495 		    xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0],      xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0]);
2498 		xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0],   xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0]);
2500 		xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0],  xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0]);
2502 		xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0],     xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0]);
2526     if (!info->accel_state->need_src_tile_x && !info->accel_state->need_src_tile_y) {
2539     modulus(srcY, info->accel_state->src_tile_height, tileSrcY);
2547 	int h = info->accel_state->src_tile_height - tileSrcY;
2553 	modulus(srcX, info->accel_state->src_tile_width, tileSrcX);
2558 	    int w = info->accel_state->src_tile_width - tileSrcX;