Lines Matching refs:save
799 RADEONSavePtr save = info->ModeReg;
803 save->bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
805 save->bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
809 save->bios_6_scratch |= RADEON_DRIVER_CRITICAL;
811 save->bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
815 OUTREG(R600_BIOS_6_SCRATCH, save->bios_6_scratch);
817 OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch);
827 RADEONSavePtr save = info->ModeReg;
832 save->bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
834 save->bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
837 save->bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
839 save->bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
842 save->bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
844 save->bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
847 save->bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
849 save->bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
852 save->bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
854 save->bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
857 save->bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
859 save->bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
862 save->bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
864 save->bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
867 save->bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
869 save->bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
872 save->bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
874 save->bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
877 save->bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
879 save->bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
882 OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch);
884 OUTREG(RADEON_BIOS_2_SCRATCH, save->bios_2_scratch);
887 save->bios_6_scratch &= ~(RADEON_DPMS_MASK | RADEON_SCREEN_BLANKING);
888 save->bios_6_scratch |= RADEON_DPMS_ON;
890 save->bios_6_scratch &= ~RADEON_DPMS_MASK;
891 save->bios_6_scratch |= (RADEON_DPMS_OFF | RADEON_SCREEN_BLANKING);
895 save->bios_6_scratch |= RADEON_TV_DPMS_ON;
897 save->bios_6_scratch &= ~RADEON_TV_DPMS_ON;
900 save->bios_6_scratch |= RADEON_CRT_DPMS_ON;
902 save->bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
905 save->bios_6_scratch |= RADEON_CRT_DPMS_ON;
907 save->bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
910 save->bios_6_scratch |= RADEON_LCD_DPMS_ON;
912 save->bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
915 save->bios_6_scratch |= RADEON_DFP_DPMS_ON;
917 save->bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
920 save->bios_6_scratch |= RADEON_DFP_DPMS_ON;
922 save->bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
924 OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch);
935 RADEONSavePtr save = info->ModeReg;
945 save->bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
946 save->bios_3_scratch |= (radeon_crtc->crtc_id << 18);
948 save->bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
949 save->bios_3_scratch |= (radeon_crtc->crtc_id << 24);
951 save->bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
952 save->bios_3_scratch |= (radeon_crtc->crtc_id << 16);
954 save->bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
955 save->bios_3_scratch |= (radeon_crtc->crtc_id << 20);
957 save->bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
958 save->bios_3_scratch |= (radeon_crtc->crtc_id << 17);
960 save->bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
961 save->bios_3_scratch |= (radeon_crtc->crtc_id << 19);
963 save->bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
964 save->bios_3_scratch |= (radeon_crtc->crtc_id << 23);
966 save->bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
967 save->bios_3_scratch |= (radeon_crtc->crtc_id << 25);
970 OUTREG(R600_BIOS_3_SCRATCH, save->bios_3_scratch);
972 OUTREG(RADEON_BIOS_3_SCRATCH, save->bios_3_scratch);
975 save->bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
976 save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_TV1_CRTC_SHIFT);
978 save->bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
979 save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_CRT1_CRTC_SHIFT);
981 save->bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
982 save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_CRT2_CRTC_SHIFT);
984 save->bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
985 save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_LCD1_CRTC_SHIFT);
987 save->bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
988 save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_DFP1_CRTC_SHIFT);
990 save->bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
991 save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_DFP2_CRTC_SHIFT);
993 OUTREG(RADEON_BIOS_5_SCRATCH, save->bios_5_scratch);
1004 RADEONSavePtr save = info->ModeReg;
1010 save->bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1012 save->bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1013 save->bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1018 save->bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1020 save->bios_0_scratch &= ~ATOM_S0_CV_MASK;
1021 save->bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1026 save->bios_0_scratch |= ATOM_S0_LCD1;
1027 save->bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1029 save->bios_0_scratch &= ~ATOM_S0_LCD1;
1030 save->bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1035 save->bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1036 save->bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1038 save->bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1039 save->bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1044 save->bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1045 save->bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1047 save->bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1048 save->bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1053 save->bios_0_scratch |= ATOM_S0_DFP1;
1054 save->bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1056 save->bios_0_scratch &= ~ATOM_S0_DFP1;
1057 save->bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1062 save->bios_0_scratch |= ATOM_S0_DFP2;
1063 save->bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1065 save->bios_0_scratch &= ~ATOM_S0_DFP2;
1066 save->bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1071 save->bios_0_scratch |= ATOM_S0_DFP3;
1072 save->bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1074 save->bios_0_scratch &= ~ATOM_S0_DFP3;
1075 save->bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1080 save->bios_0_scratch |= ATOM_S0_DFP4;
1081 save->bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1083 save->bios_0_scratch &= ~ATOM_S0_DFP4;
1084 save->bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1089 save->bios_0_scratch |= ATOM_S0_DFP5;
1090 save->bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1092 save->bios_0_scratch &= ~ATOM_S0_DFP5;
1093 save->bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1098 OUTREG(R600_BIOS_0_SCRATCH, save->bios_0_scratch);
1099 OUTREG(R600_BIOS_3_SCRATCH, save->bios_3_scratch);
1101 OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch);
1102 OUTREG(RADEON_BIOS_3_SCRATCH, save->bios_3_scratch);
1109 save->bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
1111 save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP;
1112 save->bios_5_scratch |= RADEON_TV1_ON;
1114 save->bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
1115 save->bios_5_scratch &= ~RADEON_TV1_ON;
1120 save->bios_4_scratch |= RADEON_LCD1_ATTACHED;
1121 save->bios_5_scratch |= RADEON_LCD1_ON;
1123 save->bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
1124 save->bios_5_scratch &= ~RADEON_LCD1_ON;
1129 save->bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
1130 save->bios_5_scratch |= RADEON_CRT1_ON;
1132 save->bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
1133 save->bios_5_scratch &= ~RADEON_CRT1_ON;
1138 save->bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
1139 save->bios_5_scratch |= RADEON_CRT2_ON;
1141 save->bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
1142 save->bios_5_scratch &= ~RADEON_CRT2_ON;
1147 save->bios_4_scratch |= RADEON_DFP1_ATTACHED;
1148 save->bios_5_scratch |= RADEON_DFP1_ON;
1150 save->bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
1151 save->bios_5_scratch &= ~RADEON_DFP1_ON;
1156 save->bios_4_scratch |= RADEON_DFP2_ATTACHED;
1157 save->bios_5_scratch |= RADEON_DFP2_ON;
1159 save->bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
1160 save->bios_5_scratch &= ~RADEON_DFP2_ON;
1164 OUTREG(RADEON_BIOS_4_SCRATCH, save->bios_4_scratch);
1165 OUTREG(RADEON_BIOS_5_SCRATCH, save->bios_5_scratch);
1864 .save = radeon_save,