Lines Matching refs:tmp
83 uint32_t tmp;
88 tmp = INPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV);
89 ref_div = tmp & RADEON_M_SPLL_REF_DIV_MASK;
93 tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL);
94 tmp &= ~RADEON_DONT_USE_XTALIN;
95 OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp);
97 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
98 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
99 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
103 tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
104 tmp |= RADEON_SPLL_SLEEP;
105 OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp);
109 tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
110 tmp |= RADEON_SPLL_RESET;
111 OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp);
115 tmp = INPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV);
116 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
117 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
118 OUTPLL(pScrn, RADEON_M_SPLL_REF_FB_DIV, tmp);
121 tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
122 tmp &= ~RADEON_SPLL_PVG_MASK;
124 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
126 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
127 OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp);
129 tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
130 tmp &= ~RADEON_SPLL_SLEEP;
131 OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp);
135 tmp = INPLL(pScrn, RADEON_SPLL_CNTL);
136 tmp &= ~RADEON_SPLL_RESET;
137 OUTPLL(pScrn, RADEON_SPLL_CNTL, tmp);
141 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
142 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
146 tmp |= 1;
149 tmp |= 2;
152 tmp |= 3;
155 tmp |= 4;
158 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
162 tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL);
163 tmp |= RADEON_DONT_USE_XTALIN;
164 OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp);
175 uint32_t tmp;
179 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
182 tmp &= ~(RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_RB);
184 tmp &= ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
189 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
193 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
194 tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
202 tmp |= RADEON_DYN_STOP_LAT_MASK;
203 tmp |= RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_VIP;
204 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
206 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
207 tmp &= ~RADEON_SCLK_MORE_FORCEON;
208 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
209 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
211 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
212 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
214 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
216 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
217 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
230 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
232 tmp = INPLL(pScrn, R300_SCLK_CNTL2);
233 tmp &= ~(R300_SCLK_FORCE_TCL |
236 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
239 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp);
241 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
242 tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
250 tmp |= RADEON_DYN_STOP_LAT_MASK;
251 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
253 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
254 tmp &= ~RADEON_SCLK_MORE_FORCEON;
255 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
256 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
258 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
259 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
261 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
263 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
264 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
277 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
279 tmp = INPLL(pScrn, RADEON_MCLK_MISC);
280 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
282 OUTPLL(pScrn, RADEON_MCLK_MISC, tmp);
284 tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
285 tmp |= (RADEON_FORCEON_MCLKA |
288 tmp &= ~(RADEON_FORCEON_YCLKA |
296 if ((tmp & R300_DISABLE_MC_MCLKA) &&
297 (tmp & R300_DISABLE_MC_MCLKB)) {
299 tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
302 tmp &= ~R300_DISABLE_MC_MCLKB;
304 tmp &= ~R300_DISABLE_MC_MCLKA;
306 tmp &= ~(R300_DISABLE_MC_MCLKA |
311 OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp);
313 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
314 tmp &= ~(R300_SCLK_FORCE_VAP);
315 tmp |= RADEON_SCLK_FORCE_CP;
316 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
319 tmp = INPLL(pScrn, R300_SCLK_CNTL2);
320 tmp &= ~(R300_SCLK_FORCE_TCL |
323 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp);
326 tmp = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL);
328 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
332 tmp |= (RADEON_ENGIN_DYNCLK_MODE |
334 OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, tmp);
337 tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL);
338 tmp |= RADEON_SCLK_DYN_START_CNTL;
339 OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp);
345 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
346 /*tmp &= RADEON_SCLK_SRC_SEL_MASK;*/
347 tmp &= ~RADEON_SCLK_FORCEON_MASK;
356 tmp |= RADEON_SCLK_FORCE_CP;
357 tmp |= RADEON_SCLK_FORCE_VIP;
360 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
365 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
366 tmp &= ~RADEON_SCLK_MORE_FORCEON;
373 tmp |= RADEON_SCLK_MORE_FORCEON;
375 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
384 tmp = INPLL(pScrn, RADEON_PLL_PWRMGT_CNTL);
385 tmp |= RADEON_TCL_BYPASS_DISABLE;
386 OUTPLL(pScrn, RADEON_PLL_PWRMGT_CNTL, tmp);
391 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
392 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
400 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
403 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
404 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
407 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
413 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
414 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
421 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
424 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
425 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
433 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
435 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
436 tmp |= RADEON_SCLK_MORE_FORCEON;
437 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
439 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
440 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
443 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
445 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
446 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
460 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
463 tmp = INPLL(pScrn, R300_SCLK_CNTL2);
464 tmp |= (R300_SCLK_FORCE_TCL |
467 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp);
469 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
470 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
478 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
480 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
481 tmp |= RADEON_SCLK_MORE_FORCEON;
482 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
484 tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
485 tmp |= (RADEON_FORCEON_MCLKA |
490 OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp);
492 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
493 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
496 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
498 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
499 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
513 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
515 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
516 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
517 tmp |= RADEON_SCLK_FORCE_SE;
520 tmp |= ( RADEON_SCLK_FORCE_RB |
533 tmp |= ( RADEON_SCLK_FORCE_HDP |
540 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
546 tmp = INPLL(pScrn, R300_SCLK_CNTL2);
547 tmp |= ( R300_SCLK_FORCE_TCL |
550 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp);
555 tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
556 tmp &= ~(RADEON_FORCEON_MCLKA |
558 OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp);
565 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
566 tmp |= RADEON_SCLK_MORE_FORCEON;
567 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp);
571 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
572 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
580 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
583 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL);
584 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
586 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp);
594 uint32_t tmp;
599 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
601 tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
603 tmp |= RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2;
605 tmp |= R300_SCLK_FORCE_VAP;
607 tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX;
608 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp);
610 tmp = INPLL(pScrn, AVIVO_CP_DYN_CNTL);
611 tmp |= AVIVO_CP_FORCEON;
612 OUTPLL(pScrn, AVIVO_CP_DYN_CNTL, tmp);
614 tmp = INPLL(pScrn, AVIVO_E2_DYN_CNTL);
615 tmp |= AVIVO_E2_FORCEON;
616 OUTPLL(pScrn, AVIVO_E2_DYN_CNTL, tmp);
618 tmp = INPLL(pScrn, AVIVO_IDCT_DYN_CNTL);
619 tmp |= AVIVO_IDCT_FORCEON;
620 OUTPLL(pScrn, AVIVO_IDCT_DYN_CNTL, tmp);