Lines Matching refs:save
515 RADEONSaveTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr save)
524 save->tv_uv_adr = INREG(RADEON_TV_UV_ADR);
525 hTable = RADEONGetHTimingTablesAddr(save->tv_uv_adr);
526 vTable = RADEONGetVTimingTablesAddr(save->tv_uv_adr);
539 /*OUTREG(RADEON_TV_MASTER_CNTL, save->tv_master_cntl | RADEON_TV_ON);*/
545 save->h_code_timing[ i ] = (uint16_t)((tmp >> 14) & 0x3fff);
546 save->h_code_timing[ i + 1 ] = (uint16_t)(tmp & 0x3fff);
548 if (save->h_code_timing[ i ] == 0 || save->h_code_timing[ i + 1 ] == 0)
554 save->v_code_timing[ i ] = (uint16_t)(tmp & 0x3fff);
555 save->v_code_timing[ i + 1 ] = (uint16_t)((tmp >> 14) & 0x3fff);
557 if (save->v_code_timing[ i ] == 0 || save->v_code_timing[ i + 1 ] == 0)
564 RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
571 save->tv_crc_cntl = INREG(RADEON_TV_CRC_CNTL);
572 save->tv_frestart = INREG(RADEON_TV_FRESTART);
573 save->tv_hrestart = INREG(RADEON_TV_HRESTART);
574 save->tv_vrestart = INREG(RADEON_TV_VRESTART);
575 save->tv_gain_limit_settings = INREG(RADEON_TV_GAIN_LIMIT_SETTINGS);
576 save->tv_hdisp = INREG(RADEON_TV_HDISP);
577 save->tv_hstart = INREG(RADEON_TV_HSTART);
578 save->tv_htotal = INREG(RADEON_TV_HTOTAL);
579 save->tv_linear_gain_settings = INREG(RADEON_TV_LINEAR_GAIN_SETTINGS);
580 save->tv_master_cntl = INREG(RADEON_TV_MASTER_CNTL);
581 save->tv_rgb_cntl = INREG(RADEON_TV_RGB_CNTL);
582 save->tv_modulator_cntl1 = INREG(RADEON_TV_MODULATOR_CNTL1);
583 save->tv_modulator_cntl2 = INREG(RADEON_TV_MODULATOR_CNTL2);
584 save->tv_pre_dac_mux_cntl = INREG(RADEON_TV_PRE_DAC_MUX_CNTL);
585 save->tv_sync_cntl = INREG(RADEON_TV_SYNC_CNTL);
586 save->tv_timing_cntl = INREG(RADEON_TV_TIMING_CNTL);
587 save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
588 save->tv_upsamp_and_gain_cntl = INREG(RADEON_TV_UPSAMP_AND_GAIN_CNTL);
589 save->tv_vdisp = INREG(RADEON_TV_VDISP);
590 save->tv_ftotal = INREG(RADEON_TV_FTOTAL);
591 save->tv_vscaler_cntl1 = INREG(RADEON_TV_VSCALER_CNTL1);
592 save->tv_vscaler_cntl2 = INREG(RADEON_TV_VSCALER_CNTL2);
593 save->tv_vtotal = INREG(RADEON_TV_VTOTAL);
594 save->tv_y_fall_cntl = INREG(RADEON_TV_Y_FALL_CNTL);
595 save->tv_y_rise_cntl = INREG(RADEON_TV_Y_RISE_CNTL);
596 save->tv_y_saw_tooth_cntl = INREG(RADEON_TV_Y_SAW_TOOTH_CNTL);
598 save->tv_pll_cntl = INPLL(pScrn, RADEON_TV_PLL_CNTL);
599 save->tv_pll_cntl1 = INPLL(pScrn, RADEON_TV_PLL_CNTL1);
603 RADEONSaveTVTimingTables(pScrn, save);
612 static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
676 hChanged = (p1 != save->h_code_timing[ H_TABLE_POS1 ] ||
677 p2 != save->h_code_timing[ H_TABLE_POS2 ]);
679 save->h_code_timing[ H_TABLE_POS1 ] = p1;
680 save->h_code_timing[ H_TABLE_POS2 ] = p2;
705 save->tv_hrestart = restart % hTotal;
707 save->tv_vrestart = restart % vTotal;
709 save->tv_frestart = restart % fTotal;
712 (unsigned)save->tv_frestart, (unsigned)save->tv_vrestart,
713 (unsigned)save->tv_hrestart);
725 save->tv_timing_cntl = (save->tv_timing_cntl & ~RADEON_H_INC_MASK) |
734 void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
775 save->tv_crc_cntl = 0;
777 save->tv_gain_limit_settings = (0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) |
780 save->tv_hdisp = constPtr->horResolution - 1;
781 save->tv_hstart = constPtr->horStart;
782 save->tv_htotal = constPtr->horTotal - 1;
784 save->tv_linear_gain_settings = (0x100 << RADEON_UV_GAIN_SHIFT) |
787 save->tv_master_cntl = (RADEON_VIN_ASYNC_RST
793 save->tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb;
797 save->tv_master_cntl |= RADEON_RESTART_PHASE_FIX;
799 save->tv_modulator_cntl1 = RADEON_SLEW_RATE_LIMIT
807 save->tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT)
809 save->tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) |
812 save->tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN;
813 save->tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) |
816 save->tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN
819 save->tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) |
823 save->pll_test_cntl = 0;
825 save->tv_pre_dac_mux_cntl = (RADEON_Y_RED_EN
830 save->tv_rgb_cntl = (RADEON_RGB_DITHER_EN
839 save->tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX;
841 save->tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1;
843 save->tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2;
846 save->tv_sync_cntl = RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE;
848 save->tv_sync_size = constPtr->horResolution + 8;
858 save->tv_vscaler_cntl1 = RADEON_Y_W_EN;
859 save->tv_vscaler_cntl1 =
860 (save->tv_vscaler_cntl1 & 0xe3ff0000) | (vert_space * (1 << FRAC_BITS) / 10000);
863 save->tv_vscaler_cntl1 |= RADEON_RESTART_FIELD;
866 save->tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT);
868 save->tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT);
886 save->tv_y_saw_tooth_cntl =
889 save->tv_y_fall_cntl =
893 save->tv_y_rise_cntl =
897 save->tv_vscaler_cntl2 = ((save->tv_vscaler_cntl2 & 0x00fffff0)
904 tmp = (save->tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK;
907 save->tv_timing_cntl = tmp;
913 save->tv_dac_cntl = tvdac->ntsc_tvdac_adj;
915 save->tv_dac_cntl = tvdac->pal_tvdac_adj;
917 save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD);
921 save->tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
923 save->tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
927 save->tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | RADEON_TV_DAC_GDACPD
931 save->tv_dac_cntl &= ~RADEON_TV_DAC_BDACPD;
935 save->tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
962 save->tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
968 save->tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK)<< RADEON_TVPCP_SHIFT) |
974 save->tv_upsamp_and_gain_cntl = RADEON_YUPSAMP_EN | RADEON_UVUPSAMP_EN;
976 save->tv_uv_adr = 0xc8;
978 save->tv_vdisp = constPtr->verResolution - 1;
984 save->tv_ftotal = NTSC_TV_VFTOTAL;
986 save->tv_ftotal = PAL_TV_VFTOTAL;
988 save->tv_vtotal = constPtr->verTotal - 1;
1008 if ((save->h_code_timing[ i ] = hor_timing[ i ]) == 0)
1013 if ((save->v_code_timing[ i ] = vert_timing[ i ]) == 0)
1020 RADEONInitTVRestarts(output, save, mode);
1022 save->dac_cntl &= ~RADEON_DAC_TVO_EN;
1025 save->gpiopad_a = info->SavedReg->gpiopad_a & ~1;
1028 save->disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1029 save->disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC
1032 save->disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1034 save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1037 save->disp_output_cntl &= ~RADEON_DISP_DAC_SOURCE_MASK;
1038 save->disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1041 save->disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1043 save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1076 void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
1100 save->crtc_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
1103 save->crtc_h_sync_strt_wid = (save->crtc_h_sync_strt_wid
1108 save->crtc_v_total_disp = ((constPtr->verResolution - 1) << RADEON_CRTC_V_DISP_SHIFT) |
1111 save->crtc_v_sync_strt_wid = (save->crtc_v_sync_strt_wid & ~RADEON_CRTC_V_SYNC_STRT) |
1116 void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
1141 save->htotal_cntl = (constPtr->horTotal & 0x7 /*0xf*/) | RADEON_HTOT_CNTL_VGA_EN;
1143 save->ppll_ref_div = constPtr->crtcPLL_M;
1173 save->ppll_div_3 = (constPtr->crtcPLL_N & 0x7ff) | (postDiv << 16);
1175 save->pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL);
1176 save->pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK;
1180 void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
1204 save->crtc2_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
1207 save->crtc2_h_sync_strt_wid = (save->crtc2_h_sync_strt_wid
1212 save->crtc2_v_total_disp = ((constPtr->verResolution - 1) << RADEON_CRTC_V_DISP_SHIFT) |
1215 save->crtc2_v_sync_strt_wid = (save->crtc2_v_sync_strt_wid & ~RADEON_CRTC_V_SYNC_STRT) |
1220 void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
1245 save->htotal_cntl2 = (constPtr->horTotal & 0x7); /* 0xf */
1247 save->p2pll_ref_div = constPtr->crtcPLL_M;
1277 save->p2pll_div_0 = (constPtr->crtcPLL_N & 0x7ff) | (postDiv << 16);
1279 save->pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK;
1280 save->pixclks_cntl |= (RADEON_PIX2CLK_SRC_SEL_P2PLLCLK