Lines Matching refs:tv_uv_adr
304 RADEONGetHTimingTablesAddr(uint32_t tv_uv_adr)
308 switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) {
313 hTable = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2;
316 hTable = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2;
327 RADEONGetVTimingTablesAddr(uint32_t tv_uv_adr)
331 switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) {
333 vTable = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1;
336 vTable = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1;
339 vTable = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1;
360 OUTREG(RADEON_TV_UV_ADR, restore->tv_uv_adr);
361 hTable = RADEONGetHTimingTablesAddr(restore->tv_uv_adr);
362 vTable = RADEONGetVTimingTablesAddr(restore->tv_uv_adr);
524 save->tv_uv_adr = INREG(RADEON_TV_UV_ADR);
525 hTable = RADEONGetHTimingTablesAddr(save->tv_uv_adr);
526 vTable = RADEONGetVTimingTablesAddr(save->tv_uv_adr);
976 save->tv_uv_adr = 0xc8;