Lines Matching defs:cPtr
190 static void chipsHWCursorOn(CHIPSPtr cPtr, ScrnInfoPtr pScrn);
191 static void chipsHWCursorOff(CHIPSPtr cPtr, ScrnInfoPtr pScrn);
197 static void chipsSetPanelType(CHIPSPtr cPtr);
796 CHIPSPtr cPtr;
819 cPtr = CHIPSPTR(pScrn);
820 cPtr->Chipset = match_data;
860 CHIPSPtr cPtr;
911 cPtr = CHIPSPTR(pScrn);
912 cPtr->Chipset = chipset;
1013 CHIPSPtr cPtr;
1027 cPtr = CHIPSPTR(pScrn);
1039 cPtr->pEnt = xf86GetEntityInfo(pScrn->entityList[i]);
1041 if (cPtr->pEnt->resources) return FALSE;
1046 if (!cPtr->Chipset)
1047 cPtr->Chipset = cPtr->pEnt->chipset;
1049 cPtr->pEnt->chipset);
1050 if ((cPtr->Chipset == CHIPS_CT64200) ||
1051 (cPtr->Chipset == CHIPS_CT64300)) cPtr->Flags |= ChipsWingine;
1052 if ((cPtr->Chipset >= CHIPS_CT65550) &&
1053 (cPtr->Chipset <= CHIPS_CT69030)) cPtr->Flags |= ChipsHiQV;
1056 if (cPtr->pEnt->location.type == BUS_PCI) {
1057 pciPtr = xf86GetPciInfoForEntity(cPtr->pEnt->index);
1058 cPtr->PciInfo = pciPtr;
1060 cPtr->PciTag = pciTag(cPtr->PciInfo->bus,
1061 cPtr->PciInfo->device,
1062 cPtr->PciInfo->func);
1072 pInt = xf86InitInt10(cPtr->pEnt->index);
1079 cPtr->pVbe = VBEInit(NULL,cPtr->pEnt->index);
1083 switch (cPtr->Chipset) {
1085 cPtr->Flags |= ChipsDualChannelSupport;
1087 cPtr->Flags |= ChipsFullMMIOSupport;
1090 cPtr->Flags |= ChipsImageReadSupport; /* Does the 69000 support it? */
1093 cPtr->Flags |= ChipsTMEDSupport;
1097 cPtr->Flags |= ChipsGammaSupport;
1098 cPtr->Flags |= ChipsVideoSupport;
1103 cPtr->Flags |= ChipsMMIOSupport;
1106 cPtr->Flags |= ChipsAccelSupport;
1109 cPtr->Flags |= ChipsHDepthSupport;
1110 cPtr->Flags |= ChipsDPMSSupport;
1115 cPtr->Flags |= ChipsLinearSupport;
1124 if (!(cPtr->Flags & ChipsDualChannelSupport))
1128 if (cPtr->pEnt->location.type != BUS_PCI)
1135 cPtr->entityPrivate = cPtrEnt;
1138 /* Set cPtr->device to the relevant Device section */
1139 cPtr->device = xf86GetDevFromEntity(pScrn->entityList[0],
1145 CHIPSSetStdExtFuncs(cPtr);
1148 if (IS_HiQV(cPtr))
1150 else if (IS_Wingine(cPtr))
1155 if (cPtr->UseFullMMIO)
1159 vbeFree(cPtr->pVbe);
1160 cPtr->pVbe = NULL;
1171 clockRanges->ClockMulFactor = cPtr->ClockMulFactor;
1172 clockRanges->minClock = cPtr->MinClock;
1173 clockRanges->maxClock = cPtr->MaxClock;
1175 if (cPtr->PanelType & ChipsLCD) {
1186 pScrn->videoRam -= (cPtr->FrameBufferSize + 1023) / 1024;
1188 cPtr->Rounding = 8 * (pScrn->bitsPerPixel <= 8 ? 8
1193 NULL, 256, 2048, cPtr->Rounding,
1195 pScrn->display->virtualY, cPtr->FbMapSize,
1199 vbeFree(cPtr->pVbe);
1200 cPtr->pVbe = NULL;
1208 pScrn->videoRam += (cPtr->FrameBufferSize + 1023) / 1024;
1215 vbeFree(cPtr->pVbe);
1216 cPtr->pVbe = NULL;
1245 vbeFree(cPtr->pVbe);
1246 cPtr->pVbe = NULL;
1255 vbeFree(cPtr->pVbe);
1256 cPtr->pVbe = NULL;
1264 vbeFree(cPtr->pVbe);
1265 cPtr->pVbe = NULL;
1272 if (cPtr->Flags & ChipsAccelSupport) {
1276 cPtr->Flags &= ~(ChipsAccelSupport);
1277 cPtr->Flags |= ChipsShadowFB;
1282 cPtr->Flags &= ~(ChipsAccelSupport);
1283 cPtr->Flags |= ChipsShadowFB;
1288 if (cPtr->Flags & ChipsShadowFB) {
1290 vbeFree(cPtr->pVbe);
1291 cPtr->pVbe = NULL;
1297 if (cPtr->Accel.UseHWCursor) {
1299 vbeFree(cPtr->pVbe);
1300 cPtr->pVbe = NULL;
1307 if (cPtr->Flags & ChipsLinearSupport)
1308 xf86SetOperatingState(resVgaMem, cPtr->pEnt->index, ResDisableOpr);
1310 if (cPtr->MMIOBaseVGA)
1311 xf86SetOperatingState(resVgaIo, cPtr->pEnt->index, ResDisableOpr);
1314 vbeFree(cPtr->pVbe);
1315 cPtr->pVbe = NULL;
1333 CHIPSPtr cPtr = CHIPSPTR(pScrn);
1335 CHIPSPanelSizePtr Size = &cPtr->PanelSize;
1336 CHIPSMemClockPtr MemClk = &cPtr->MemClock;
1337 CHIPSClockPtr SaveClk = &(cPtr->SavedReg.Clock);
1390 cPtr->PIOBase = hwp->PIOOffset;
1392 cPtr->PIOBase = 0;
1399 if ((cPtr->Flags & ChipsDualChannelSupport) &&
1401 vgaHWAllocDefaultRegs(&(cPtr->VgaSavedReg2));
1435 if (!(cPtr->Options = malloc(sizeof(ChipsHiQVOptions))))
1437 memcpy(cPtr->Options, ChipsHiQVOptions, sizeof(ChipsHiQVOptions));
1438 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, cPtr->Options);
1444 if (xf86GetOptValInteger(cPtr->Options, OPTION_RGB_BITS, &val)) {
1454 if ((cPtr->Flags & ChipsAccelSupport) &&
1455 (xf86ReturnOptValBool(cPtr->Options, OPTION_NOACCEL, FALSE))) {
1456 cPtr->Flags &= ~ChipsAccelSupport;
1463 cPtr->Accel.UseHWCursor = FALSE;
1465 cPtr->Accel.UseHWCursor = TRUE;
1467 if (xf86GetOptValBool(cPtr->Options, OPTION_HW_CURSOR,
1468 &cPtr->Accel.UseHWCursor))
1470 if (xf86GetOptValBool(cPtr->Options, OPTION_SW_CURSOR,
1471 &cPtr->Accel.UseHWCursor)) {
1473 cPtr->Accel.UseHWCursor = !cPtr->Accel.UseHWCursor;
1476 (cPtr->Accel.UseHWCursor) ? "HW" : "SW");
1480 if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, FALSE)) {
1481 cPtr->Flags &= ~ChipsLinearSupport;
1484 } else if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, TRUE)) {
1485 cPtr->Flags &= ~ChipsLinearSupport;
1490 if (!(cPtr->Flags & ChipsLinearSupport)) {
1497 if (cPtr->Flags & ChipsLinearSupport) {
1498 if (cPtr->pEnt->location.type == BUS_PCI) {
1501 if (BE_SWAP_APRETURE(pScrn,cPtr))
1502 cPtr->FbAddress = (PCI_REGION_BASE(cPtr->PciInfo, 0, REGION_MEM) & 0xff800000) + 0x800000L;
1505 cPtr->FbAddress = PCI_REGION_BASE(cPtr->PciInfo, 0, REGION_MEM) & 0xff800000;
1509 if (xf86RegisterResources(cPtr->pEnt->index,NULL,ResNone))
1510 cPtr->Flags &= ~ChipsLinearSupport;
1513 if (cPtr->pEnt->device->MemBase) {
1514 cPtr->FbAddress = cPtr->pEnt->device->MemBase;
1517 cPtr->FbAddress = ((unsigned int)
1518 (cPtr->readXR(cPtr, 0x06))) << 24;
1519 cPtr->FbAddress |= ((unsigned int)
1520 (0x80 & (cPtr->readXR(cPtr, 0x05)))) << 16;
1524 linearRes[0].rBegin = cPtr->FbAddress;
1525 linearRes[0].rEnd = cPtr->FbAddress + 0x800000;
1526 if (xf86RegisterResources(cPtr->pEnt->index,linearRes,ResNone)) {
1527 cPtr->Flags &= ~ChipsLinearSupport;
1533 if (cPtr->Flags & ChipsLinearSupport) {
1537 "base address is set at 0x%lX.\n", cPtr->FbAddress);
1539 if (BE_SWAP_APRETURE(pScrn,cPtr))
1540 cPtr->IOAddress = cPtr->FbAddress - 0x400000L;
1543 cPtr->IOAddress = cPtr->FbAddress + 0x400000L;
1545 "IOAddress is set at 0x%lX.\n",(unsigned long)cPtr->IOAddress);
1551 if ((s = xf86GetOptValString(cPtr->Options, OPTION_ROTATE))
1552 || xf86ReturnOptValBool(cPtr->Options, OPTION_SHADOW_FB, FALSE)) {
1553 if (!(cPtr->Flags & ChipsLinearSupport)) {
1560 cPtr->Rotate = 0;
1564 cPtr->Flags |= ChipsShadowFB;
1565 cPtr->Rotate = 1;
1569 cPtr->Flags |= ChipsShadowFB;
1570 cPtr->Rotate = -1;
1582 cPtr->Flags |= ChipsShadowFB;
1587 if(xf86GetOptValInteger(cPtr->Options, OPTION_VIDEO_KEY,
1588 &(cPtr->videoKey))) {
1590 cPtr->videoKey);
1592 cPtr->videoKey = (1 << pScrn->offset.red) |
1598 if (cPtr->Flags & ChipsShadowFB) {
1599 if (cPtr->Flags & ChipsAccelSupport) {
1602 cPtr->Flags &= ~ChipsAccelSupport;
1604 if (cPtr->Rotate && cPtr->Accel.UseHWCursor) {
1607 cPtr->Accel.UseHWCursor = FALSE;
1611 if (xf86ReturnOptValBool(cPtr->Options, OPTION_MMIO, TRUE)) {
1612 cPtr->UseMMIO = TRUE;
1617 if (xf86ReturnOptValBool(cPtr->Options, OPTION_FULL_MMIO, FALSE)) {
1618 if ((cPtr->Flags & ChipsLinearSupport)
1619 && (cPtr->Flags & ChipsFullMMIOSupport)
1620 && (cPtr->pEnt->location.type == BUS_PCI)) {
1624 cPtr->UseFullMMIO = TRUE;
1634 cPtr->FbMapSize = 1024 * 1024;
1641 if (cPtr->MMIOBaseVGA) {
1642 CHIPSSetMmioExtFuncs(cPtr);
1643 CHIPSHWSetMmioFuncs(pScrn, cPtr->MMIOBaseVGA, 0x0);
1653 cPtr->UseMMIO = FALSE;
1654 cPtr->Accel.UseHWCursor = FALSE;
1655 cPtr->Flags &= ~ChipsAccelSupport;
1659 if (cPtr->Flags & ChipsDualChannelSupport) {
1675 * secondary CRTC from the screen field in cPtr->pEnt->device.
1679 if (cPtr->pEnt->device->screen == 1)
1684 cPtr->SecondCrtc = TRUE;
1685 cPtr->UseDualChannel = TRUE;
1687 cPtr->SecondCrtc = FALSE;
1690 if (xf86ReturnOptValBool(cPtr->Options,
1692 cPtr->Flags |= ChipsDualRefresh;
1695 cPtr->UseDualChannel = TRUE;
1700 cPtr->storeIOSS = cPtr->readIOSS(cPtr);
1701 cPtr->storeMSS = cPtr->readMSS(cPtr);
1706 if (cPtr->pEnt->device->videoRam != 0) {
1707 pScrn->videoRam = cPtr->pEnt->device->videoRam;
1712 switch (cPtr->Chipset) {
1716 cPtr->Flags |= Chips64BitMemory;
1721 cPtr->Flags |= Chips64BitMemory;
1730 switch (((cPtr->readXR(cPtr, 0x43)) & 0x06) >> 1) {
1749 tmp = (cPtr->readXR(cPtr, 0xE0)) & 0xF;
1774 tmp = cPtr->readXR(cPtr, 0x43);
1776 cPtr->Flags |= Chips64BitMemory;
1782 if (cPtr->pEnt->chipset == CHIPS_CT69030 && ((cPtr->readXR(cPtr, 0x71) & 0x2)) == 0) /* CFG9: Pipeline variable ByteSwap mapping */
1783 cPtr->dualEndianAp = TRUE;
1785 cPtr->dualEndianAp = FALSE;
1788 if ((cPtr->Flags & ChipsDualChannelSupport) &&
1794 pScrn->memPhysBase = cPtr->FbAddress;
1796 if(cPtr->SecondCrtc == FALSE) {
1799 xf86GetOptValInteger(cPtr->Options, OPTION_CRT2_MEM, &crt2mem);
1814 cPtrEnt->masterFbAddress = cPtr->FbAddress;
1815 cPtr->FbMapSize =
1820 cPtrEnt->slaveFbAddress = cPtr->FbAddress +
1822 cPtr->FbMapSize = cPtrEnt->slaveFbMapSize;
1830 cPtr->FbMapSize = pScrn->videoRam * 1024;
1838 cPtr->SuspendHack.vgaIOBaseFlag = ((hwp->readMiscOut(hwp)) & 0x01);
1839 cPtr->IOBase = (unsigned int)(cPtr->SuspendHack.vgaIOBaseFlag ?
1850 if (cPtr->pVbe) {
1852 = xf86PrintEDID(vbeDoEDID(cPtr->pVbe, pVbeModule))) != NULL) {
1862 cPtr->I2C))) != NULL) {
1880 tmp = cPtr->readFR(cPtr, 0x10);
1887 if (xf86ReturnOptValBool(cPtr->Options, OPTION_STN, FALSE)) {
1888 cPtr->PanelType |= ChipsSS;
1891 cPtr->PanelType |= ChipsTFT;
1896 cPtr->PanelType |= ChipsDS;
1899 cPtr->PanelType |= ChipsDD;
1906 chipsSetPanelType(cPtr);
1910 if (xf86GetOptValBool(cPtr->Options, OPTION_FP_MODE, &fp_mode)) {
1913 cPtr->PanelType |= ChipsLCD;
1916 cPtr->PanelType = ~ChipsLCD;
1921 if ((cPtr->PanelType & ChipsLCD) && (cPtr->PanelType & ChipsCRT))
1923 else if (cPtr->PanelType & ChipsLCD)
1925 else if (cPtr->PanelType & ChipsCRT) {
1929 cPtr->Monitor = chipsSetMonitor(pScrn);
1937 if (cPtr->PanelType & ChipsLCD) {
1945 fr25 = cPtr->readFR(cPtr, 0x25);
1946 tmp = cPtr->readFR(cPtr, 0x20);
1948 tmp = cPtr->readFR(cPtr, 0x30);
1949 tmp1 = cPtr->readFR(cPtr, 0x35);
1952 tmp = cPtr->readFR(cPtr, 0x21);
1954 tmp1 = cPtr->readFR(cPtr, 0x22);
1958 tmp = cPtr->readFR(cPtr, 0x23);
1959 fr26 = cPtr->readFR(cPtr, 0x26);
1971 if (xf86ReturnOptValBool(cPtr->Options, OPTION_PANEL_SIZE, FALSE)) {
1978 if (IS_STN(cPtr->PanelType)) {
1979 tmp = cPtr->readFR(cPtr, 0x1A); /*Frame Buffer Ctrl. */
1987 cPtr->FrameBufferSize = ( Size->HDisplay *
1991 cPtr->FrameBufferSize);
2002 tmp = (cPtr->readXR(cPtr, 0x08)) & 1;
2005 cPtr->Bus = ChipsPCI;
2008 cPtr->Bus = ChipsVLB;
2015 cPtr->Flags &= ~ChipsAccelSupport;
2021 if ((pScrn->bitsPerPixel == 8) || ((cPtr->Chipset >= CHIPS_CT65555) &&
2023 cPtr->Flags |= ChipsColorTransparency;
2025 cPtr->Flags &= ~ChipsColorTransparency;
2028 if (!((cPtr->readXR(cPtr, 0xD0)) & 0x01))
2032 cPtr->Regs32 = ChipsReg32HiQV;
2035 cPtr->SyncResetIgn = TRUE; /* !! */
2040 cPtr->ClockType = HiQV_STYLE | TYPE_PROGRAMMABLE;
2047 switch (cPtr->Chipset) {
2049 if (((cPtr->readXR(cPtr, 0x04)) & 0xF) < 6)
2072 tmp = cPtr->readXR(cPtr,0xC2 + offset);
2073 M = (cPtr->readXR(cPtr, 0xC0 + offset)
2075 N = (cPtr->readXR(cPtr, 0xC1 + offset)
2077 tmp = cPtr->readXR(cPtr, 0xC3 + offset);
2078 PSN = (cPtr->Chipset == CHIPS_CT69000 || cPtr->Chipset == CHIPS_CT69030)
2080 VCO_D = ((tmp & 0x04) ? ((cPtr->Chipset == CHIPS_CT69000 ||
2081 cPtr->Chipset == CHIPS_CT69030) ? 1 : 16) : 4);
2089 if (cPtr->Chipset == CHIPS_CT69030)
2090 FPclkI = (cPtr->readFR(cPtr, 0x01) >> 2) & 0x3;
2092 FPclkI = (cPtr->readFR(cPtr, 0x03) >> 2) & 0x3;
2102 cPtr->FPclock = Probed[FPclkI];
2103 cPtr->FPclkInx = FPclkI;
2110 cPtr->CRTclkInx = CRTclkI;
2117 if (xf86GetOptValInteger(cPtr->Options, OPTION_CRT_CLK_INDX, &indx)) {
2120 cPtr->CRTclkInx = indx;
2122 if (xf86GetOptValInteger(cPtr->Options, OPTION_FP_CLK_INDX, &indx)) {
2125 cPtr->FPclkInx = indx;
2127 if (indx == cPtr->FPclkInx) {
2129 cPtr->FPclkInx = 1;
2131 cPtr->FPclkInx = indx + 1;
2133 "FP Clock index forced to %d\n", cPtr->FPclkInx);
2136 } else if (xf86GetOptValInteger(cPtr->Options, OPTION_FP_CLK_INDX,
2140 cPtr->FPclkInx = indx;
2141 if (indx == cPtr->CRTclkInx) {
2143 cPtr->CRTclkInx = 1;
2145 cPtr->CRTclkInx = indx + 1;
2147 "CRT Clock index forced to %d\n", cPtr->CRTclkInx);
2153 MemClk->xrCC = cPtr->readXR(cPtr, 0xCC);
2155 MemClk->xrCD = cPtr->readXR(cPtr, 0xCD);
2157 MemClk->xrCE = cPtr->readXR(cPtr, 0xCE);
2167 if (xf86GetOptValFreq(cPtr->Options, OPTION_SET_MCLK, OPTUNITS_MHZ, &real)) {
2200 cPtr->ClockMulFactor = 1;
2203 switch (cPtr->Chipset) {
2205 cPtr->MinClock = 3000;
2206 cPtr->MaxClock = 170000;
2209 cPtr->MinClock = 3000;
2210 cPtr->MaxClock = 135000;
2214 cPtr->MinClock = 1000;
2215 cPtr->MaxClock = 110000;
2218 cPtr->MinClock = 1000;
2219 cPtr->MaxClock = 95000;
2222 cPtr->MinClock = 1000;
2223 if (((cPtr->readXR(cPtr, 0x04)) & 0xF) < 6) {
2224 if ((cPtr->readFR(cPtr, 0x0A)) & 2) {
2226 cPtr->MaxClock = 100000;
2229 cPtr->MaxClock = 80000;
2232 cPtr->MaxClock = 95000; /* Revision B */
2236 (float)(cPtr->MinClock / 1000.));
2243 if (cPtr->Flags & Chips64BitMemory) {
2244 if (cPtr->FrameBufferSize && (cPtr->PanelType & ChipsLCD))
2245 cPtr->MaxClock = min(cPtr->MaxClock,
2248 cPtr->MaxClock = min(cPtr->MaxClock,
2251 if (cPtr->FrameBufferSize && (cPtr->PanelType & ChipsLCD))
2252 cPtr->MaxClock = min(cPtr->MaxClock,
2255 cPtr->MaxClock = min(cPtr->MaxClock,
2261 if (cPtr->pEnt->device->dacSpeeds[0]) {
2267 speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP8];
2270 speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP16];
2273 speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP24];
2276 speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP32];
2281 speed = cPtr->pEnt->device->dacSpeeds[0];
2285 (float)(speed / 1000.), (float)(cPtr->MaxClock / 1000.));
2286 cPtr->MaxClock = speed;
2290 (float)(cPtr->MaxClock / 1000.));
2300 if (xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_8, OPTUNITS_MHZ, &real))
2305 if (xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_16, OPTUNITS_MHZ, &real))
2310 if (xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_24, OPTUNITS_MHZ, &real))
2315 if (xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_32, OPTUNITS_MHZ, &real))
2321 if (val && val >= cPtr->MinClock && val <= cPtr->MaxClock)
2322 cPtr->FPclock = val;
2323 else if (cPtr->FPclock > cPtr->MaxClock)
2324 cPtr->FPclock = (int)((float)cPtr->MaxClock * 0.9);
2326 cPtr->FPclock = 0; /* special value */
2327 cPtr->FPClkModified = FALSE;
2328 if (cPtr->FPclock)
2331 (float)(cPtr->FPclock / 1000.));
2339 if (cPtr->Flags & ChipsDualChannelSupport) {
2341 if (cPtr->SecondCrtc == TRUE) {
2348 cPtr->writeIOSS(cPtr, cPtr->storeIOSS);
2349 cPtr->writeMSS(cPtr, hwp, cPtr->storeMSS);
2364 CHIPSPtr cPtr = CHIPSPTR(pScrn);
2365 CHIPSClockPtr SaveClk = &(cPtr->SavedReg.Clock);
2375 if (cPtr->Flags & ChipsHDepthSupport)
2394 if (cPtr->Flags & ChipsHDepthSupport)
2450 cPtr->SuspendHack.xr02 = (cPtr->readXR(cPtr, 0x02)) & 0x18;
2451 cPtr->SuspendHack.xr03 = (cPtr->readXR(cPtr, 0x03)) & 0x0A;
2452 cPtr->SuspendHack.xr14 = (cPtr->readXR(cPtr, 0x14)) & 0x20;
2453 cPtr->SuspendHack.xr15 = cPtr->readXR(cPtr, 0x15);
2455 cPtr->SuspendHack.vgaIOBaseFlag = ((hwp->readMiscOut(hwp)) & 0x01);
2456 cPtr->IOBase = (unsigned int)(cPtr->SuspendHack.vgaIOBaseFlag ?
2465 if (!(cPtr->Options = malloc(sizeof(ChipsWingineOptions))))
2467 memcpy(cPtr->Options, ChipsWingineOptions, sizeof(ChipsWingineOptions));
2468 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, cPtr->Options);
2475 if (xf86GetOptValInteger(cPtr->Options, OPTION_RGB_BITS,
2482 if ((cPtr->Flags & ChipsAccelSupport) &&
2483 (xf86ReturnOptValBool(cPtr->Options, OPTION_NOACCEL, FALSE))) {
2484 cPtr->Flags &= ~ChipsAccelSupport;
2491 cPtr->Accel.UseHWCursor = FALSE;
2493 cPtr->Accel.UseHWCursor = TRUE;
2495 if (xf86GetOptValBool(cPtr->Options, OPTION_HW_CURSOR,
2496 &cPtr->Accel.UseHWCursor))
2498 if (xf86GetOptValBool(cPtr->Options, OPTION_SW_CURSOR,
2499 &cPtr->Accel.UseHWCursor)) {
2501 cPtr->Accel.UseHWCursor = !cPtr->Accel.UseHWCursor;
2504 (cPtr->Accel.UseHWCursor) ? "HW" : "SW");
2507 if (cPtr->pEnt->device->videoRam != 0) {
2508 pScrn->videoRam = cPtr->pEnt->device->videoRam;
2520 switch ((cPtr->readXR(cPtr, 0x0F)) & 3) {
2537 cPtr->FbMapSize = pScrn->videoRam * 1024;
2540 if (cPtr->Flags & ChipsLinearSupport) useLinear = TRUE;
2542 if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, FALSE)) {
2546 } else if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, TRUE)) {
2552 if (!(cPtr->Flags & ChipsLinearSupport)) {
2565 if (cPtr->pEnt->device->MemBase) {
2566 cPtr->FbAddress = cPtr->pEnt->device->MemBase
2570 cPtr->FbAddress = ((0xFF & (cPtr->readXR(cPtr, 0x09))) << 24);
2571 cPtr->FbAddress |= ((mask & (cPtr->readXR(cPtr, 0x08))) << 16);
2575 linearRes[0].rBegin = cPtr->FbAddress;
2576 linearRes[0].rEnd = cPtr->FbAddress + 0x800000;
2577 if (xf86RegisterResources(cPtr->pEnt->index,linearRes,ResNone)) {
2588 "base address is set at 0x%lX.\n", cPtr->FbAddress);
2589 if (xf86ReturnOptValBool(cPtr->Options, OPTION_MMIO, FALSE) &&
2590 (cPtr->Flags & ChipsMMIOSupport)) {
2591 cPtr->UseMMIO = TRUE;
2592 cPtr->IOAddress = cPtr->FbAddress + 0x200000L;
2596 if (cPtr->Flags & ChipsLinearSupport)
2599 cPtr->Flags &= ~ChipsLinearSupport;
2602 if ((s = xf86GetOptValString(cPtr->Options, OPTION_ROTATE))
2603 || xf86ReturnOptValBool(cPtr->Options, OPTION_SHADOW_FB, FALSE)) {
2604 if (!(cPtr->Flags & ChipsLinearSupport)) {
2611 cPtr->Rotate = 0;
2615 cPtr->Flags |= ChipsShadowFB;
2616 cPtr->Rotate = 1;
2620 cPtr->Flags |= ChipsShadowFB;
2621 cPtr->Rotate = -1;
2633 cPtr->Flags |= ChipsShadowFB;
2637 if (cPtr->Flags & ChipsShadowFB) {
2638 if (cPtr->Flags & ChipsAccelSupport) {
2641 cPtr->Flags &= ~ChipsAccelSupport;
2643 if (cPtr->Rotate && cPtr->Accel.UseHWCursor) {
2646 cPtr->Accel.UseHWCursor = FALSE;
2650 cPtr->PanelType |= ChipsCRT;
2654 cPtr->Monitor = chipsSetMonitor(pScrn);
2657 tmp = cPtr->readXR(cPtr, 0x01) & 3;
2661 cPtr->Bus = ChipsISA;
2665 cPtr->Bus = ChipsVLB;
2669 cPtr->Bus = ChipsUnknown;
2677 cPtr->Flags &= ~ChipsAccelSupport;
2681 if ((cPtr->Flags & ChipsAccelSupport) ||
2682 (cPtr->Accel.UseHWCursor)) {
2683 cPtr->Regs32 = xnfalloc(sizeof(ChipsReg32));
2684 tmp = cPtr->readXR(cPtr, 0x07);
2686 cPtr->Regs32[i] = ((ChipsReg32[i] & 0x7E03)) | ((tmp & 0x80)
2689 ErrorF("DR[%X] = %X\n",i,cPtr->Regs32[i]);
2694 linearRes[0].rBase = cPtr->Regs32[0];
2696 if (xf86RegisterResources(cPtr->pEnt->index,linearRes,ResNone)) {
2697 if (cPtr->Flags & ChipsAccelSupport) {
2698 cPtr->Flags &= ~ChipsAccelSupport;
2703 if (cPtr->Accel.UseHWCursor) {
2704 cPtr->Accel.UseHWCursor = FALSE;
2713 cPtr->ClockMulFactor = ((pScrn->bitsPerPixel >= 8) ? bytesPerPixel : 1);
2714 if (cPtr->ClockMulFactor != 1)
2716 "Clocks scaled by %d\n", cPtr->ClockMulFactor);
2719 switch (cPtr->Chipset) {
2722 cPtr->ClockType = WINGINE_1_STYLE | TYPE_HW;
2725 if (!((cPtr->readXR(cPtr, 0x01)) & 0x10)) {
2729 cPtr->ClockType = WINGINE_1_STYLE | TYPE_HW;
2733 if (xf86ReturnOptValBool(cPtr->Options, OPTION_HW_CLKS, FALSE)) {
2735 cPtr->ClockType = WINGINE_2_STYLE | TYPE_HW;
2738 cPtr->ClockType = WINGINE_2_STYLE | TYPE_PROGRAMMABLE;
2744 if (cPtr->ClockType & TYPE_PROGRAMMABLE) {
2752 if (!cPtr->pEnt->device->numclocks) {
2756 cPtr->IOBase + 0x0A, 0x08, 1, 28322);
2759 pScrn->numClocks = cPtr->pEnt->device->numclocks;
2768 pScrn->clock[i] = cPtr->pEnt->device->clock[i];
2776 cPtr->MinClock = 11000 / cPtr->ClockMulFactor;
2778 (float)(cPtr->MinClock / 1000.));
2780 switch (cPtr->Chipset) {
2782 cPtr->MaxClock = 80000 / cPtr->ClockMulFactor;
2785 cPtr->MaxClock = 85000 / cPtr->ClockMulFactor;
2789 if (cPtr->pEnt->device->dacSpeeds[0]) {
2795 speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP8];
2798 speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP16];
2801 speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP24];
2805 cPtr->MaxClock = cPtr->pEnt->device->dacSpeeds[0];
2809 (float)(cPtr->MaxClock / 1000.), (float)(speed / 1000.));
2810 cPtr->MaxClock = speed;
2814 (float)(cPtr->MaxClock / 1000.));
2818 if (cPtr->pVbe)
2819 xf86SetDDCproperties(pScrn,xf86PrintEDID(vbeDoEDID(cPtr->pVbe, NULL)));
2831 CHIPSPtr cPtr = CHIPSPTR(pScrn);
2832 CHIPSPanelSizePtr Size = &cPtr->PanelSize;
2833 CHIPSClockPtr SaveClk = &(cPtr->SavedReg.Clock);
2843 if (cPtr->Flags & ChipsHDepthSupport)
2862 if (cPtr->Flags & ChipsHDepthSupport)
2917 cPtr->SuspendHack.xr02 = (cPtr->readXR(cPtr, 0x02)) & 0x18;
2918 cPtr->SuspendHack.xr03 = (cPtr->readXR(cPtr, 0x03)) & 0x0A;
2919 cPtr->SuspendHack.xr14 = (cPtr->readXR(cPtr, 0x14)) & 0x20;
2920 cPtr->SuspendHack.xr15 = cPtr->readXR(cPtr, 0x15);
2922 cPtr->SuspendHack.vgaIOBaseFlag = ((hwp->readMiscOut(hwp)) & 0x01);
2923 cPtr->IOBase = cPtr->SuspendHack.vgaIOBaseFlag ? 0x3D0 : 0x3B0;
2931 if (!(cPtr->Options = malloc(sizeof(Chips655xxOptions))))
2933 memcpy(cPtr->Options, Chips655xxOptions, sizeof(Chips655xxOptions));
2934 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, cPtr->Options);
2941 if (xf86GetOptValInteger(cPtr->Options, OPTION_RGB_BITS,
2948 if ((cPtr->Flags & ChipsAccelSupport) &&
2949 (xf86ReturnOptValBool(cPtr->Options, OPTION_NOACCEL, FALSE))) {
2950 cPtr->Flags &= ~ChipsAccelSupport;
2957 cPtr->Accel.UseHWCursor = FALSE;
2959 cPtr->Accel.UseHWCursor = TRUE;
2961 if (xf86GetOptValBool(cPtr->Options, OPTION_HW_CURSOR,
2962 &cPtr->Accel.UseHWCursor))
2964 if (xf86GetOptValBool(cPtr->Options, OPTION_SW_CURSOR,
2965 &cPtr->Accel.UseHWCursor)) {
2967 cPtr->Accel.UseHWCursor = !cPtr->Accel.UseHWCursor;
2970 (cPtr->Accel.UseHWCursor) ? "HW" : "SW");
2973 if (cPtr->pEnt->device->videoRam != 0) {
2974 pScrn->videoRam = cPtr->pEnt->device->videoRam;
2986 switch ((cPtr->readXR(cPtr, 0x0F)) & 3) {
3002 cPtr->FbMapSize = pScrn->videoRam * 1024;
3005 if (cPtr->Flags & ChipsLinearSupport) useLinear = TRUE;
3007 if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, FALSE)) {
3011 } else if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, TRUE)) {
3017 if (!(cPtr->Flags & ChipsLinearSupport)) {
3026 if (cPtr->Chipset == CHIPS_CT65535) {
3028 if (cPtr->Bus == ChipsISA)
3030 } else if (cPtr->Bus == ChipsISA) {
3034 tmp = cPtr->readXR(cPtr, 0x01);
3040 if (cPtr->pEnt->location.type == BUS_PCI) {
3041 cPtr->FbAddress = PCI_REGION_BASE(cPtr->PciInfo, 0, REGION_MEM) & 0xff800000;
3043 if (xf86RegisterResources(cPtr->pEnt->index,NULL,ResNone)) {
3049 if (cPtr->pEnt->device->MemBase) {
3050 cPtr->FbAddress = cPtr->pEnt->device->MemBase;
3051 if (cPtr->Chipset == CHIPS_CT65535)
3052 cPtr->FbAddress &= (mask << 17);
3053 else if (cPtr->Chipset > CHIPS_CT65535)
3054 cPtr->FbAddress &= (mask << 20);
3057 if (cPtr->Chipset <= CHIPS_CT65530) {
3060 cPtr->FbAddress = 0xC00000;
3062 } else if (cPtr->Chipset == CHIPS_CT65535) {
3063 cPtr->FbAddress =
3064 ((mask & (cPtr->readXR(cPtr, 0x08))) << 17);
3066 cPtr->FbAddress =
3067 ((mask & (cPtr->readXR(cPtr, 0x08))) << 20);
3072 linearRes[0].rBegin = cPtr->FbAddress;
3073 linearRes[0].rEnd = cPtr->FbAddress + 0x800000;
3074 if (xf86RegisterResources(cPtr->pEnt->index,linearRes,ResNone)) {
3086 "base address is set at 0x%lX.\n", cPtr->FbAddress);
3087 if (xf86ReturnOptValBool(cPtr->Options, OPTION_MMIO, FALSE) &&
3088 (cPtr->Flags & ChipsMMIOSupport)) {
3089 cPtr->UseMMIO = TRUE;
3090 cPtr->IOAddress = cPtr->FbAddress + 0x200000L;
3094 if (cPtr->Flags & ChipsLinearSupport)
3097 cPtr->Flags &= ~ChipsLinearSupport;
3100 if ((s = xf86GetOptValString(cPtr->Options, OPTION_ROTATE))
3101 || xf86ReturnOptValBool(cPtr->Options, OPTION_SHADOW_FB, FALSE)) {
3102 if (!(cPtr->Flags & ChipsLinearSupport)) {
3109 cPtr->Rotate = 0;
3113 cPtr->Flags |= ChipsShadowFB;
3114 cPtr->Rotate = 1;
3118 cPtr->Flags |= ChipsShadowFB;
3119 cPtr->Rotate = -1;
3131 cPtr->Flags |= ChipsShadowFB;
3135 if (cPtr->Flags & ChipsShadowFB) {
3136 if (cPtr->Flags & ChipsAccelSupport) {
3139 cPtr->Flags &= ~ChipsAccelSupport;
3141 if (cPtr->Rotate && cPtr->Accel.UseHWCursor) {
3144 cPtr->Accel.UseHWCursor = FALSE;
3149 tmp = cPtr->readXR(cPtr, 0x51);
3156 if (xf86ReturnOptValBool(cPtr->Options, OPTION_STN, FALSE)) {
3157 cPtr->PanelType |= ChipsSS;
3160 cPtr->PanelType |= ChipsTFT;
3165 cPtr->PanelType |= ChipsDS;
3168 cPtr->PanelType |= ChipsDD;
3175 chipsSetPanelType(cPtr);
3179 if (xf86GetOptValBool(cPtr->Options, OPTION_FP_MODE, &fp_mode)) {
3182 cPtr->PanelType |= ChipsLCD;
3185 cPtr->PanelType = ~ChipsLCD;
3190 if ((cPtr->PanelType & ChipsLCD) && (cPtr->PanelType & ChipsCRT))
3192 else if (cPtr->PanelType & ChipsLCD)
3194 else if (cPtr->PanelType & ChipsCRT) {
3197 cPtr->Monitor = chipsSetMonitor(pScrn);
3205 if (cPtr->PanelType & ChipsLCD) {
3209 xr17 = cPtr->readXR(cPtr, 0x17);
3210 tmp = cPtr->readXR(cPtr, 0x1B);
3212 tmp = cPtr->readXR(cPtr, 0x1C);
3214 tmp = cPtr->readXR(cPtr, 0x19);
3216 tmp1 = cPtr->readXR(cPtr, 0x1A);
3220 tmp1 = cPtr->readXR(cPtr, 0x65);
3221 tmp = cPtr->readXR(cPtr, 0x68);
3224 tmp = cPtr->readXR(cPtr, 0x66);
3227 tmp = cPtr->readXR(cPtr, 0x64);
3241 if (xf86ReturnOptValBool(cPtr->Options, OPTION_PANEL_SIZE, FALSE)) {
3248 if (IS_STN(cPtr->PanelType)) {
3249 tmp = cPtr->readXR(cPtr, 0x6F); /*Frame Buffer Ctrl. */
3252 if ((cPtr->Chipset > CHIPS_CT65530) && !(tmp & 0x80)) {
3257 cPtr->FrameBufferSize = ( Size->HDisplay *
3261 cPtr->FrameBufferSize);
3272 if (cPtr->Chipset > CHIPS_CT65535) {
3273 tmp = (cPtr->readXR(cPtr, 0x01)) & 7;
3276 cPtr->Bus = ChipsPCI;
3277 if ((cPtr->Chipset == CHIPS_CT65545) ||
3278 (cPtr->Chipset == CHIPS_CT65546)) {
3282 cPtr->UseMMIO = TRUE;
3283 cPtr->IOAddress = cPtr->FbAddress + 0x200000L;
3290 cPtr->Bus = ChipsCPUDirect;
3294 cPtr->Bus = ChipsISA;
3298 cPtr->Bus = ChipsVLB;
3305 tmp = (cPtr->readXR(cPtr, 0x01)) & 3;
3309 cPtr->Bus = ChipsPIB;
3313 cPtr->Bus = ChipsMCB;
3317 cPtr->Bus = ChipsVLB;
3321 cPtr->Bus = ChipsISA;
3326 if (!(cPtr->Bus == ChipsPCI) && (cPtr->UseMMIO)) {
3327 cPtr->UseMMIO = FALSE;
3336 cPtr->Flags &= ~ChipsAccelSupport;
3339 if ((cPtr->Chipset == CHIPS_CT65530) &&
3340 (cPtr->Flags & ChipsLinearSupport)) {
3344 if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LINEAR, FALSE))
3345 cPtr->Flags &= ~ChipsLinearSupport;
3352 if ((cPtr->Bus == ChipsISA) && (pScrn->videoRam > 512)) {
3355 cPtr->Flags &= ~ChipsLinearSupport;
3360 if ((cPtr->readXR(cPtr, 0x06)) & 0x02)
3364 if (cPtr->UseMMIO)
3365 cPtr->Regs32 = ChipsReg32;
3366 else if ((cPtr->Flags & ChipsAccelSupport) ||
3367 (cPtr->Accel.UseHWCursor)) {
3368 cPtr->Regs32 = xnfalloc(sizeof(ChipsReg32));
3369 tmp = cPtr->readXR(cPtr, 0x07);
3371 cPtr->Regs32[i] =
3375 ErrorF("DR[%X] = %X\n",i,cPtr->Regs32[i]);
3380 linearRes[0].rBase = cPtr->Regs32[0];
3382 if (xf86RegisterResources(cPtr->pEnt->index,linearRes,ResNone)) {
3383 if (cPtr->Flags & ChipsAccelSupport) {
3384 cPtr->Flags &= ~ChipsAccelSupport;
3389 if (cPtr->Accel.UseHWCursor) {
3390 cPtr->Accel.UseHWCursor = FALSE;
3400 if (cPtr->Chipset > CHIPS_CT65530) {
3401 tmp = cPtr->readXR(cPtr, 0x0E);
3403 cPtr->SyncResetIgn = TRUE;
3406 (cPtr->SyncResetIgn ? "" : "not "));
3409 cPtr->ClockMulFactor = ((pScrn->bitsPerPixel >= 8) ? bytesPerPixel : 1);
3410 if (cPtr->ClockMulFactor != 1)
3412 "Clocks scaled by %d\n", cPtr->ClockMulFactor);
3414 switch (cPtr->Chipset) {
3419 cPtr->ClockType = OLD_STYLE | TYPE_HW;
3422 if (xf86ReturnOptValBool(cPtr->Options, OPTION_HW_CLKS, FALSE)) {
3424 cPtr->ClockType = NEW_STYLE | TYPE_HW;
3427 cPtr->ClockType = NEW_STYLE | TYPE_PROGRAMMABLE;
3432 if (cPtr->ClockType & TYPE_PROGRAMMABLE) {
3434 SaveClk->Clock = ((cPtr->PanelType & ChipsLCDProbed) ?
3441 if (!cPtr->pEnt->device->numclocks) {
3445 cPtr->IOBase + 0x0A, 0x08, 1, 28322);
3448 pScrn->numClocks = cPtr->pEnt->device->numclocks;
3457 pScrn->clock[i] = cPtr->pEnt->device->clock[i];
3464 cPtr->MinClock = 11000 / cPtr->ClockMulFactor;
3466 (float)(cPtr->MinClock / 1000.));
3468 switch (cPtr->Chipset) {
3473 cPtr->MaxClock = 80000 / cPtr->ClockMulFactor;
3476 if ((cPtr->readXR(cPtr, 0x6C)) & 2) {
3478 cPtr->MaxClock = 68000 / cPtr->ClockMulFactor;
3481 cPtr->MaxClock = 56000 / cPtr->ClockMulFactor;
3485 if (cPtr->pEnt->device->dacSpeeds[0]) {
3491 speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP8];
3494 speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP16];
3497 speed = cPtr->pEnt->device->dacSpeeds[DAC_BPP24];
3501 cPtr->MaxClock = cPtr->pEnt->device->dacSpeeds[0];
3505 (float)(cPtr->MaxClock / 1000.), (float)(speed / 1000.));
3506 cPtr->MaxClock = speed;
3510 (float)(cPtr->MaxClock / 1000.));
3514 if (cPtr->ClockType & TYPE_PROGRAMMABLE) {
3519 xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_8,
3523 xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_16,
3527 xf86GetOptValFreq(cPtr->Options, OPTION_FP_CLOCK_24,
3537 if (val && (val >= cPtr->MinClock)
3538 && (val <= cPtr->MaxClock))
3539 cPtr->FPclock = val * cPtr->ClockMulFactor;
3540 else if (val > cPtr->MaxClock)
3541 cPtr->FPclock = (int)((float)cPtr->MaxClock
3542 * cPtr->ClockMulFactor * 0.9);
3544 cPtr->FPclock = 0; /* special value */
3546 cPtr->FPclock = 0; /* special value */
3548 if (cPtr->FPclock)
3551 (float)(cPtr->FPclock / 1000.));
3553 if (xf86IsOptionSet(cPtr->Options, OPTION_SET_MCLK))
3559 if (cPtr->ClockType & TYPE_PROGRAMMABLE) {
3562 switch (cPtr->Chipset) {
3566 cPtr->MemClock.Max = 75000;
3569 if ((cPtr->readXR(cPtr, 0x6C)) & 2) {
3571 cPtr->MemClock.Max = 68000;
3574 cPtr->MemClock.Max = 56000;
3578 if (xf86GetOptValFreq(cPtr->Options, OPTION_SET_MCLK,
3581 if (mclk <= cPtr->MemClock.Max) {
3585 cPtr->MemClock.Clk = mclk;
3590 (float)(cPtr->MemClock.Max/1000.));
3591 cPtr->MemClock.Clk = cPtr->MemClock.Max * 0.9;
3594 cPtr->MemClock.Clk = 0;
3596 if (xf86IsOptionSet(cPtr->Options, OPTION_SET_MCLK))
3601 if (cPtr->pVbe)
3602 xf86SetDDCproperties(pScrn,xf86PrintEDID(vbeDoEDID(cPtr->pVbe, NULL)));
3613 CHIPSPtr cPtr = CHIPSPTR(pScrn);
3616 if (cPtr->Flags & ChipsDualChannelSupport) {
3624 if ((cPtr->Flags & ChipsVideoSupport)
3625 && (cPtr->Flags & ChipsLinearSupport))
3629 chipsHWCursorOn(cPtr, pScrn);
3642 CHIPSPtr cPtr = CHIPSPTR(pScrn);
3651 if (cPtr->Flags & ChipsDualChannelSupport) {
3654 if (cPtr->UseDualChannel)
3658 chipsHWCursorOff(cPtr, pScrn);
3659 chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg, &cPtr->SavedReg,
3675 CHIPSPtr cPtr = CHIPSPTR(pScrn);
3681 if (cPtr->UseDualChannel) {
3699 if (cPtr->UseDualChannel &&
3702 IOSS = cPtr->readIOSS(cPtr);
3703 MSS = cPtr->readMSS(cPtr);
3704 cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
3706 cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) | MSS_PIPE_B));
3719 cPtr->writeIOSS(cPtr, IOSS);
3720 cPtr->writeMSS(cPtr, hwp, MSS);
3732 CHIPSPtr cPtr = CHIPSPTR(pScrn);
3737 if (cPtr->UseDualChannel) {
3756 if (cPtr->UseDualChannel &&
3759 IOSS = cPtr->readIOSS(cPtr);
3760 MSS = cPtr->readMSS(cPtr);
3761 cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
3763 cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) | MSS_PIPE_B));
3777 cPtr->writeIOSS(cPtr, IOSS);
3778 cPtr->writeMSS(cPtr, hwp, MSS);
3791 CHIPSPtr cPtr;
3811 cPtr = CHIPSPTR(pScrn);
3828 if (cPtr->UseFullMMIO && cPtr->MMIOBaseVGA) {
3829 CHIPSSetMmioExtFuncs(cPtr);
3830 CHIPSHWSetMmioFuncs(pScrn, cPtr->MMIOBaseVGA, 0x0);
3833 if (cPtr->Flags & ChipsDualChannelSupport) {
3842 cPtr->TVMode = XMODE_PAL;
3846 cPtr->TVMode = XMODE_SECAM;
3850 cPtr->TVMode = XMODE_NTSC;
3852 cPtr->TVMode = XMODE_RGB;
3858 if ((cPtr->Flags & ChipsDualChannelSupport) &&
3861 IOSS = cPtr->readIOSS(cPtr);
3862 MSS = cPtr->readMSS(cPtr);
3863 cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
3865 cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) | MSS_PIPE_A));
3866 chipsSave(pScrn, &hwp->SavedReg, &cPtr->SavedReg);
3867 cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
3869 cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) | MSS_PIPE_B));
3870 chipsSave(pScrn, &cPtr->VgaSavedReg2, &cPtr->SavedReg2);
3871 cPtr->writeIOSS(cPtr, IOSS);
3872 cPtr->writeMSS(cPtr, hwp, MSS);
3874 chipsSave(pScrn, &hwp->SavedReg, &cPtr->SavedReg);
3909 if ((cPtr->Flags & ChipsShadowFB) && cPtr->Rotate) {
3917 if(cPtr->Flags & ChipsShadowFB) {
3918 cPtr->ShadowPitch = BitmapBytePad(pScrn->bitsPerPixel * width);
3919 cPtr->ShadowPtr = malloc(cPtr->ShadowPitch * height);
3920 displayWidth = cPtr->ShadowPitch / (pScrn->bitsPerPixel >> 3);
3921 FBStart = cPtr->ShadowPtr;
3923 cPtr->ShadowPtr = NULL;
3925 FBStart = cPtr->FbBase;
3994 cPtr->BlockHandler = pScreen->BlockHandler;
4000 cPtr->HWCursorShown = FALSE;
4003 if (!(cPtr->Flags & ChipsLinearSupport)) {
4012 cPtr->Bank = -1;
4019 if (IS_HiQV(cPtr)) {
4038 if (IS_Wingine(cPtr)) {
4087 allocatebase = (pScrn->videoRam<<10) - cPtr->FrameBufferSize;
4096 if ((cPtr->Flags & ChipsDualChannelSupport) &&
4097 (cPtr->SecondCrtc == TRUE)) {
4113 if (IS_HiQV(cPtr)) {
4119 } else if (IS_Wingine(cPtr)) {
4135 if (cPtr->Flags & ChipsAccelSupport) {
4159 if (!IS_HiQV(cPtr)) {
4172 if (IS_HiQV(cPtr)) {
4193 if (IS_HiQV(cPtr))
4194 cAcl->BltDataWindow = (unsigned char *)cPtr->MMIOBase
4197 cAcl->BltDataWindow = cPtr->FbBase;
4216 if (cPtr->Flags & ChipsAccelSupport) {
4217 if (IS_HiQV(cPtr)) {
4225 else if (cPtr->UseMMIO) {
4250 if (cPtr->Flags & ChipsShadowFB) {
4253 if(cPtr->Rotate) {
4254 if (!cPtr->PointerMoved) {
4255 cPtr->PointerMoved = pScrn->PointerMoved;
4290 if ((cPtr->Flags & ChipsVideoSupport)
4291 && (cPtr->Flags & ChipsLinearSupport)) {
4298 if (cPtr->Flags & ChipsDPMSSupport)
4303 cPtr->CloseScreen = pScreen->CloseScreen;
4319 CHIPSPtr cPtr = CHIPSPTR(pScrn);
4325 if (cPtr->UseDualChannel) {
4339 CHIPSPtr cPtr = CHIPSPTR(pScrn);
4346 if (xf86ReturnOptValBool(cPtr->Options, OPTION_SHOWCACHE, FALSE) && y) {
4347 int lastline = cPtr->FbMapSize /
4366 if (!IS_HiQV(cPtr))
4378 if (cPtr->UseDualChannel) {
4391 if (IS_HiQV(cPtr)) {
4392 if (((cPtr->readXR(cPtr, 0x09)) & 0x1) == 0x1)
4395 tmp = cPtr->readXR(cPtr, 0x0C);
4396 cPtr->writeXR(cPtr, 0x0C, ((Base & (IS_Wingine(cPtr) ? 0x0F0000 :
4400 if (cPtr->UseDualChannel &&
4403 IOSS = cPtr->readIOSS(cPtr);
4404 MSS = cPtr->readMSS(cPtr);
4405 cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
4407 cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) | MSS_PIPE_B));
4412 if (((cPtr->readXR(cPtr, 0x09)) & 0x1) == 0x1)
4415 cPtr->writeIOSS(cPtr, IOSS);
4416 cPtr->writeMSS(cPtr, hwp, MSS);
4426 CHIPSPtr cPtr = CHIPSPTR(pScrn);
4430 if (cPtr->Flags & ChipsDualChannelSupport) {
4433 if (cPtr->UseDualChannel)
4437 chipsHWCursorOff(cPtr, pScrn);
4438 chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg, &cPtr->SavedReg,
4456 if (cPtr->AccelInfoRec)
4457 XAADestroyInfoRec(cPtr->AccelInfoRec);
4459 if (cPtr->CursorInfoRec)
4460 xf86DestroyCursorInfoRec(cPtr->CursorInfoRec);
4461 free(cPtr->ShadowPtr);
4462 free(cPtr->DGAModes);
4464 if(cPtr->BlockHandler)
4465 pScreen->BlockHandler = cPtr->BlockHandler;
4467 pScreen->CloseScreen = cPtr->CloseScreen; /*§§§*/
4487 CHIPSPtr cPtr = CHIPSPTR(pScrn);
4490 if ((mode->Flags & V_INTERLACE) && (cPtr->PanelType & ChipsLCD))
4492 if ((cPtr->PanelType & ChipsLCD)
4493 && !xf86ReturnOptValBool(cPtr->Options, OPTION_PANEL_SIZE, FALSE)
4494 && ((cPtr->PanelSize.HDisplay < mode->HDisplay)
4495 || (cPtr->PanelSize.VDisplay < mode->VDisplay)))
4517 CHIPSPtr cPtr = CHIPSPTR(pScrn);
4557 if (cPtr->UseDualChannel) {
4565 if (IS_HiQV(cPtr)) {
4566 tmp = cPtr->readXR(cPtr, 0x61);
4567 cPtr->writeXR(cPtr, 0x61, (tmp & 0xF0) | dpmsreg);
4569 tmp = cPtr->readXR(cPtr, 0x73);
4570 cPtr->writeXR(cPtr, 0x73, (tmp & 0xF0) | dpmsreg);
4574 if (cPtr->PanelType & ChipsLCDProbed) {
4575 if (IS_HiQV(cPtr)) {
4576 if (cPtr->Chipset == CHIPS_CT69030) {
4579 tmp = cPtr->readFR(cPtr, 0x05);
4581 cPtr->writeFR(cPtr, 0x05, tmp | 0x08);
4583 cPtr->writeFR(cPtr, 0x05, tmp & 0xF7);
4586 tmp = cPtr->readFR(cPtr, 0x05);
4588 cPtr->writeFR(cPtr, 0x05, tmp | 0x08);
4590 cPtr->writeFR(cPtr, 0x05, tmp & 0xF7);
4593 tmp = cPtr->readXR(cPtr, 0x52);
4595 cPtr->writeXR(cPtr, 0x52, tmp | 0x08);
4597 cPtr->writeXR(cPtr, 0x52, tmp & 0xF7);
4626 CHIPSPtr cPtr = CHIPSPTR(pScrn);
4630 chipsClockSave(pScrn, &cPtr->SaveClock);
4634 chipsClockLoad(pScrn, &cPtr->SaveClock);
4668 CHIPSPtr cPtr = CHIPSPTR(pScrn);
4669 unsigned char Type = cPtr->ClockType;
4677 if (cPtr->UseDualChannel) {
4683 if (cPtr->Flags & ChipsDualChannelSupport)
4684 Clock->fr03 = cPtr->readFR(cPtr, 0x01);
4686 Clock->fr03 = cPtr->readFR(cPtr, 0x03);
4688 tmp = cPtr->CRTclkInx << 2;
4689 cPtr->CRTClk[0] = cPtr->readXR(cPtr, 0xC0 + tmp);
4690 cPtr->CRTClk[1] = cPtr->readXR(cPtr, 0xC1 + tmp);
4691 cPtr->CRTClk[2] = cPtr->readXR(cPtr, 0xC2 + tmp);
4692 cPtr->CRTClk[3] = cPtr->readXR(cPtr, 0xC3 + tmp);
4693 tmp = cPtr->FPclkInx << 2;
4694 cPtr->FPClk[0] = cPtr->readXR(cPtr, 0xC0 + tmp);
4695 cPtr->FPClk[1] = cPtr->readXR(cPtr, 0xC1 + tmp);
4696 cPtr->FPClk[2] = cPtr->readXR(cPtr, 0xC2 + tmp);
4697 cPtr->FPClk[3] = cPtr->readXR(cPtr, 0xC3 + tmp);
4702 Clock->xr02 = cPtr->readXR(cPtr, 0x02);
4703 Clock->xr54 = cPtr->readXR(cPtr, 0x54); /* save alternate clock select reg.*/
4709 Clock->xr54 = cPtr->readXR(cPtr, 0x54); /* save alternate clock select reg.*/
4710 Clock->xr33 = cPtr->readXR(cPtr, 0x33); /* get status of MCLK/VCLK sel reg.*/
4723 CHIPSPtr cPtr = CHIPSPTR(pScrn);
4724 unsigned char Type = cPtr->ClockType;
4730 if (cPtr->UseDualChannel) {
4738 Clock->msr = cPtr->CRTclkInx << 2;
4739 Clock->fr03 = cPtr->FPclkInx << 2;
4741 if (xf86ReturnOptValBool(cPtr->Options, OPTION_USE_MODELINE, FALSE)) {
4744 Clock->FPClock = cPtr->FPclock;
4766 chipsSetPanelType(cPtr);
4769 if (cPtr->Options
4770 && xf86GetOptValBool(cPtr->Options, OPTION_FP_MODE, &fp_m)) {
4772 cPtr->PanelType |= ChipsLCD;
4774 cPtr->PanelType = ~ChipsLCD;
4778 if ((cPtr->PanelType & ChipsLCD) && cPtr->FPclock)
4779 Clock->Clock = cPtr->FPclock;
4823 CHIPSPtr cPtr = CHIPSPTR(pScrn);
4824 unsigned char Type = cPtr->ClockType;
4837 if (!(cPtr->PanelType & ChipsLCDProbed))
4840 tmp = cPtr->readXR(cPtr, 0x54);
4842 if (!(cPtr->PanelType & ChipsLCDProbed))
4849 tmp1 = cPtr->readXR(cPtr, 0x02);
4853 if (cPtr->PanelType & ChipsLCDProbed) {
4854 tmp = cPtr->readXR(cPtr, 0x54);
4859 tmp1 = cPtr->readXR(cPtr, 0x33);
4871 CHIPSPtr cPtr = CHIPSPTR(pScrn);
4872 unsigned char Type = cPtr->ClockType;
4883 if (cPtr->Flags & ChipsDualChannelSupport) {
4884 tmpf03 = cPtr->readFR(cPtr, 0x01);
4886 tmpf03 = cPtr->readFR(cPtr, 0x03);
4889 cPtr->SuspendHack.vgaIOBaseFlag);
4891 if (cPtr->Flags & ChipsDualChannelSupport) {
4892 cPtr->writeFR(cPtr, 0x01, (tmpf03 & ~0x0C) | 0x04);
4894 cPtr->writeFR(cPtr, 0x03, (tmpf03 & ~0x0C) | 0x04);
4896 tmp = cPtr->CRTclkInx << 2;
4897 cPtr->writeXR(cPtr, 0xC0 + tmp, (cPtr->CRTClk[0] & 0xFF));
4898 cPtr->writeXR(cPtr, 0xC1 + tmp, (cPtr->CRTClk[1] & 0xFF));
4899 cPtr->writeXR(cPtr, 0xC2 + tmp, (cPtr->CRTClk[2] & 0xFF));
4900 cPtr->writeXR(cPtr, 0xC3 + tmp, (cPtr->CRTClk[3] & 0xFF));
4902 if (cPtr->FPClkModified) {
4904 tmp = cPtr->FPclkInx << 2;
4905 cPtr->writeXR(cPtr, 0xC0 + tmp, (cPtr->FPClk[0] & 0xFF));
4906 cPtr->writeXR(cPtr, 0xC1 + tmp, (cPtr->FPClk[1] & 0xFF));
4907 cPtr->writeXR(cPtr, 0xC2 + tmp, (cPtr->FPClk[2] & 0xFF));
4908 cPtr->writeXR(cPtr, 0xC3 + tmp, (cPtr->FPClk[3] & 0xFF));
4916 tmp = cPtr->CRTclkInx << 2;
4917 cPtr->writeXR(cPtr, 0xC0 + tmp, (vclk[1] & 0xFF));
4918 cPtr->writeXR(cPtr, 0xC1 + tmp, (vclk[2] & 0xFF));
4919 cPtr->writeXR(cPtr, 0xC2 + tmp, 0x0);
4920 cPtr->writeXR(cPtr, 0xC3 + tmp, (vclk[0] & 0xFF));
4924 tmp = cPtr->FPclkInx << 2;
4925 cPtr->writeXR(cPtr, 0xC0 + tmp, (vclk[1] & 0xFF));
4926 cPtr->writeXR(cPtr, 0xC1 + tmp, (vclk[2] & 0xFF));
4927 cPtr->writeXR(cPtr, 0xC2 + tmp, 0x0);
4928 cPtr->writeXR(cPtr, 0xC3 + tmp, (vclk[0] & 0xFF));
4929 cPtr->FPClkModified = TRUE;
4934 if (cPtr->Flags & ChipsDualChannelSupport) {
4935 cPtr->writeFR(cPtr, 0x01, ((tmpf03 & ~0x0C) |
4938 cPtr->writeFR(cPtr, 0x03, ((tmpf03 & ~0x0C) |
4948 cPtr->SuspendHack.vgaIOBaseFlag);
4950 tmp33 = cPtr->readXR(cPtr, 0x33); /* get status of MCLK/VCLK select reg */
4951 cPtr->writeXR(cPtr, 0x33, tmp33 & ~0x20);
4952 cPtr->writeXR(cPtr, 0x30, vclk[0]);
4953 cPtr->writeXR(cPtr, 0x31, vclk[1]); /* restore VCLK regs. */
4954 cPtr->writeXR(cPtr, 0x32, vclk[2]);
4955 /* cPtr->writeXR(cPtr, 0x33, tmp33 & ~0x20);*/
4960 tmp02 = cPtr->readXR(cPtr, 0x02);
4961 tmp54 = cPtr->readXR(cPtr, 0x54);
4963 cPtr->writeXR(cPtr, 0x02, ((tmp02 & ~0x02) | (Clock->xr02 & 0x02)));
4964 cPtr->writeXR(cPtr, 0x54, ((tmp54 & 0xF0) | (Clock->xr54 & ~0xF0)));
4968 tmp33 = cPtr->readXR(cPtr, 0x33); /* get status of MCLK/VCLK select reg */
4969 tmp54 = cPtr->readXR(cPtr, 0x54);
4974 cPtr->SuspendHack.vgaIOBaseFlag);
4975 cPtr->writeXR(cPtr, 0x54, (tmp54 & 0xF3));
4977 if (cPtr->MemClock.Clk) {
4978 chipsCalcClock(pScrn, cPtr->MemClock.Clk, vclk);
4980 cPtr->writeXR(cPtr, 0x33, tmp33 | 0x20);
4981 cPtr->writeXR(cPtr, 0x30, vclk[0]);
4982 cPtr->writeXR(cPtr, 0x31, vclk[1]);
4983 cPtr->writeXR(cPtr, 0x32, vclk[2]);
4987 cPtr->writeXR(cPtr, 0x33, tmp33 & ~0x20);
4988 cPtr->writeXR(cPtr, 0x30, vclk[0]);
4989 cPtr->writeXR(cPtr, 0x31, vclk[1]); /* restore VCLK regs. */
4990 cPtr->writeXR(cPtr, 0x32, vclk[2]);
4991 /* cPtr->writeXR(cPtr, 0x33, tmp33 & ~0x20);*/
4994 cPtr->writeXR(cPtr, 0x33, ((tmp33 & ~0x80) | (Clock->xr33 & 0x80)));
4995 cPtr->writeXR(cPtr, 0x54, ((tmp54 & 0xF3) | (Clock->xr54 & ~0xF3)));
4999 cPtr->SuspendHack.vgaIOBaseFlag);
5013 CHIPSPtr cPtr = CHIPSPTR(pScrn);
5029 int M_max = (IS_HiQV(cPtr) && cPtr->Chipset != CHIPS_CT69000 &&
5030 cPtr->Chipset != CHIPS_CT69030) ? 63 : 127;
5071 for (PSNx = ((cPtr->Chipset == CHIPS_CT69000) ||
5072 (cPtr->Chipset == CHIPS_CT69030)) ? 1 : 0; PSNx <= 1; PSNx++) {
5081 while (Fref / (PSN * low_N) > (((cPtr->Chipset == CHIPS_CT69000) ||
5082 (cPtr->Chipset == CHIPS_CT69030)) ? 5.0e6 : 2.0e6))
5092 for (P = (IS_HiQV(cPtr) && (cPtr->Chipset != CHIPS_CT69000) &&
5093 (cPtr->Chipset != CHIPS_CT69030)) ? 1 : 0;
5115 if (Fvco <= ((cPtr->Chipset == CHIPS_CT69000 ||
5116 cPtr->Chipset == CHIPS_CT69030) ? 100.0e6 : 48.0e6))
5141 vclk[0] = (bestP << (IS_HiQV(cPtr) ? 4 : 1)) +
5142 (((cPtr->Chipset == CHIPS_CT69000) || (cPtr->Chipset == CHIPS_CT69030))
5157 CHIPSPtr cPtr = CHIPSPTR(pScrn);
5166 if (IS_HiQV(cPtr)) {
5167 cPtr->writeXR(cPtr, 0x0E, 0x00);
5169 cPtr->writeXR(cPtr, 0x10, 0x00);
5170 cPtr->writeXR(cPtr, 0x11, 0x00);
5171 tmp = cPtr->readXR(cPtr, 0x0C) & ~0x50; /* WINgine stores MSB here */
5172 cPtr->writeXR(cPtr, 0x0C, tmp);
5175 tmp = cPtr->readXR(cPtr, 0x02);
5176 cPtr->writeXR(cPtr, 0x02, tmp & ~0x18);
5187 if (IS_HiQV(cPtr)) {
5192 cPtr->writeXR(cPtr, 0x4E, 0x04);
5194 ChipsSave->XR[i] = cPtr->readXR(cPtr,i);
5200 ChipsSave->FR[i] = cPtr->readFR(cPtr, i);
5206 ChipsSave->MR[i] = cPtr->readMR(cPtr, i);
5221 ChipsSave->XR[i] = cPtr->readXR(cPtr, i);
5232 CHIPSPtr cPtr = CHIPSPTR(pScrn);
5244 if (cPtr->Accel.UseHWCursor)
5245 cPtr->Flags |= ChipsHWCursor;
5247 cPtr->Flags &= ~ChipsHWCursor;
5252 cPtr->cursorDelay = TRUE;
5254 if (IS_HiQV(cPtr))
5256 else if (IS_Wingine(cPtr))
5300 CHIPSPtr cPtr = CHIPSPTR(pScrn);
5305 ChipsNew = &cPtr->ModeReg;
5313 if (xf86ReturnOptValBool(cPtr->Options, OPTION_PANEL_SIZE, FALSE)) {
5314 cPtr->PanelSize.HDisplay = mode->CrtcHDisplay;
5315 cPtr->PanelSize.VDisplay = mode->CrtcVDisplay;
5333 if (cPtr->UseDualChannel && ((cPtr->SecondCrtc == TRUE) ||
5334 (cPtr->Flags & ChipsDualRefresh))) {
5337 ((cPtr->FrameBufferSize && (cPtr->PanelType & ChipsLCD)) ?
5338 1 : 0)) / (8 * 0.7)) > cPtr->MemClock.Max) {
5351 cPtr->writeXR(cPtr, 0x4E, 0x04);
5353 ChipsNew->XR[i] = cPtr->readXR(cPtr, i);
5356 ChipsNew->FR[i] = cPtr->readFR(cPtr, i);
5359 ChipsNew->MR[i] = cPtr->readMR(cPtr, i);
5398 if (!(cPtr->Flags & ChipsLinearSupport) || (pScrn->bitsPerPixel < 8))
5404 if (!cPtr->dualEndianAp)
5424 if ((cPtr->MemClock.Clk - cPtr->MemClock.ProbedClk) > 50U) {
5426 ChipsNew->XR[0xCC] = cPtr->MemClock.xrCC;
5427 ChipsNew->XR[0xCD] = cPtr->MemClock.xrCD;
5428 ChipsNew->XR[0xCE] = cPtr->MemClock.xrCE;
5432 if (cPtr->Flags & ChipsDualChannelSupport) {
5434 if ((cPtr->SecondCrtc == FALSE) && (cPtr->PanelType & ChipsLCD))
5439 if ((cPtr->SecondCrtc == TRUE) || (cPtr->Flags & ChipsDualRefresh))
5444 if (cPtr->PanelType & ChipsLCD)
5446 if (cPtr->PanelType & ChipsCRT)
5451 if (cPtr->Flags & ChipsLinearSupport) {
5455 (unsigned char)((cPtr->FbAddress >> 16) & 0xFF);
5457 (unsigned char)((cPtr->FbAddress >> 24) & 0xFF);
5462 if (xf86ReturnOptValBool(cPtr->Options, OPTION_USE_MODELINE, FALSE)) {
5464 lcdHDisplay = (cPtr->PanelSize.HDisplay >> 3) - 1;
5470 lcdVDisplay = cPtr->PanelSize.VDisplay - 1;
5503 if ((cPtr->Chipset == CHIPS_CT69000) || (cPtr->Chipset == CHIPS_CT69030)) {
5514 if (!xf86ReturnOptValBool(cPtr->Options, OPTION_SUSPEND_HACK, FALSE)) {
5515 if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LCD_STRETCH, FALSE)) {
5523 if (cPtr->Accel.UseHWCursor
5524 && cPtr->PanelSize.HDisplay && cPtr->PanelSize.VDisplay
5525 && (cPtr->PanelSize.HDisplay != mode->CrtcHDisplay)
5526 && (cPtr->PanelSize.VDisplay != mode->CrtcVDisplay)) {
5527 if(cPtr->Accel.UseHWCursor)
5530 cPtr->Flags &= ~ChipsHWCursor;
5535 if (xf86ReturnOptValBool(cPtr->Options, OPTION_LCD_CENTER, TRUE)) {
5544 if (xf86ReturnOptValBool(cPtr->Options, OPTION_SYNC_ON_GREEN, FALSE))
5548 ChipsNew->XR[0xE2] = chipsVideoMode((pScrn->depth), (cPtr->PanelType & ChipsLCD) ?
5549 min(mode->CrtcHDisplay, cPtr->PanelSize.HDisplay) :
5588 if (cPtr->Flags & ChipsGammaSupport)
5597 if (cPtr->Flags & ChipsGammaSupport)
5603 if (cPtr->Flags & ChipsGammaSupport)
5610 if (!(cPtr->PanelType & ChipsLCD)) {
5631 if (cPtr->TVMode != XMODE_RGB) {
5635 xf86SetTVOut(cPtr->TVMode);
5643 if (cPtr->TVMode == XMODE_PAL || cPtr->TVMode == XMODE_SECAM) {
5657 if (IS_STN(cPtr->PanelType)) {
5662 if ((cPtr->Flags & ChipsTMEDSupport) &&
5663 !xf86ReturnOptValBool(cPtr->Options, OPTION_NO_TMED, FALSE)) {
5668 if (cPtr->PanelType & ChipsDD) /* Shift Clock Mask. Use to get */
5679 if (cPtr->PanelType & ChipsLCD) {
5680 cPtr->OverlaySkewX = (((ChipsNew->FR[0x23] & 0xFF)
5683 cPtr->OverlaySkewY = (ChipsNew->FR[0x33]
5688 if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LCD_STRETCH, FALSE)
5689 && xf86ReturnOptValBool(cPtr->Options, OPTION_LCD_CENTER, TRUE))
5691 if (cPtr->PanelSize.HDisplay > mode->CrtcHDisplay)
5692 cPtr->OverlaySkewX += (cPtr->PanelSize.HDisplay -
5694 if (cPtr->PanelSize.VDisplay > mode->CrtcVDisplay)
5695 cPtr->OverlaySkewY += (cPtr->PanelSize.VDisplay -
5699 cPtr->OverlaySkewX = mode->CrtcHTotal - mode->CrtcHBlankStart - 9;
5700 cPtr->OverlaySkewY = mode->CrtcVTotal - mode->CrtcVSyncEnd - 1;
5709 cPtr->OverlaySkewY += 5;
5712 cPtr->OverlaySkewY *= 2;
5721 cPtr->viewportMask = ~7U;
5724 cPtr->viewportMask = ~3U;
5727 cPtr->viewportMask = ~7U;
5730 cPtr->viewportMask = ~0U;
5733 cPtr->viewportMask = ~7U;
5739 if (cPtr->Flags & ChipsVideoSupport) {
5747 cPtr->VideoZoomMax = 0x100;
5749 if (cPtr->Chipset == CHIPS_CT65550) {
5750 tmp = cPtr->readXR(cPtr, 0x04);
5752 cPtr->VideoZoomMax = 0x40; /* 0x40 max zoom */
5759 if (cPtr->Chipset <= CHIPS_CT69000) {
5761 if (cPtr->PanelType & ChipsLCD)
5766 if ((cPtr->Flags & ChipsDualChannelSupport) &&
5771 IOSS = cPtr->readIOSS(cPtr);
5772 MSS = cPtr->readMSS(cPtr);
5773 cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
5775 cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) |
5778 cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
5780 cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) |
5787 if (cPtr->UseDualChannel)
5791 cPtr->writeIOSS(cPtr, IOSS);
5792 cPtr->writeMSS(cPtr, hwp, MSS);
5808 CHIPSPtr cPtr = CHIPSPTR(pScrn);
5813 ChipsNew = &cPtr->ModeReg;
5867 ChipsNew->XR[i] = cPtr->readXR(cPtr, i);
5944 if (cPtr->Flags & ChipsLinearSupport) {
5950 (unsigned char)((cPtr->FbAddress >> 16) & 0xFF);
5952 (unsigned char)((cPtr->FbAddress >> 24) & 0xFF);
6035 CHIPSPtr cPtr = CHIPSPTR(pScrn);
6040 ChipsNew = &cPtr->ModeReg;
6049 if (xf86ReturnOptValBool(cPtr->Options, OPTION_PANEL_SIZE, FALSE)) {
6050 cPtr->PanelSize.HDisplay = mode->CrtcHDisplay;
6051 cPtr->PanelSize.VDisplay = mode->CrtcVDisplay;
6109 ChipsNew->XR[i] = cPtr->readXR(cPtr, i);
6165 if (!(cPtr->PanelType & ChipsLCD)) {
6182 if (!xf86ReturnOptValBool(cPtr->Options, OPTION_USE_MODELINE, FALSE)) {
6183 lcdHTotal = cPtr->PanelSize.HTotal;
6184 lcdHRetraceStart = cPtr->PanelSize.HRetraceStart;
6185 lcdHRetraceEnd = cPtr->PanelSize.HRetraceEnd;
6208 lcdHDisplay = cPtr->PanelSize.HDisplay;
6252 if (xf86ReturnOptValBool(cPtr->Options, OPTION_USE_MODELINE, FALSE)) {
6261 lcdVDisplay = cPtr->PanelSize.VDisplay - 1;
6285 tmp = ((cPtr->PanelType & ChipsDD) && !(ChipsNew->XR[0x6F] & 0x02))
6296 if ((unsigned)ChipsNew->XR[0x2C] < ((cPtr->PanelSize.VTotal -
6297 cPtr->PanelSize.VRetraceStart - tmp - 1) -
6308 if (!xf86ReturnOptValBool(cPtr->Options, OPTION_SUSPEND_HACK, FALSE)) {
6312 if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LCD_STRETCH,
6326 if (!xf86ReturnOptValBool(cPtr->Options, OPTION_LCD_STRETCH,
6330 tmp = (mode->CrtcVDisplay / (cPtr->PanelSize.VDisplay -
6333 if (cPtr->PanelSize.HDisplay
6334 && cPtr->PanelSize.VDisplay
6335 && (cPtr->PanelSize.HDisplay != mode->CrtcHDisplay)
6336 && (cPtr->PanelSize.VDisplay != mode->CrtcVDisplay)) {
6338 if(cPtr->Accel.UseHWCursor)
6341 cPtr->Flags &= ~ChipsHWCursor;
6344 if (cPtr->Flags & ChipsHWCursor)
6355 ChipsNew->XR[0x2B] = chipsVideoMode(pScrn->depth, (cPtr->PanelType & ChipsLCD) ?
6356 min(HDisplay, cPtr->PanelSize.HDisplay) : HDisplay,cPtr->PanelSize.VDisplay);
6362 if (cPtr->Flags & ChipsLinearSupport) {
6366 if (cPtr->Chipset == CHIPS_CT65535)
6367 ChipsNew->XR[0x08] = (unsigned char)(cPtr->FbAddress >> 17);
6368 else if (cPtr->Chipset > CHIPS_CT65535)
6369 ChipsNew->XR[0x08] = (unsigned char)(cPtr->FbAddress >> 20);
6374 if (cPtr->Bus == ChipsISA)
6394 if (cPtr->Bus == ChipsPCI)
6451 if (xf86ReturnOptValBool(cPtr->Options, OPTION_18_BIT_BUS, FALSE)) {
6459 if (!(cPtr->PanelType & ChipsLCD)) {
6465 if(cPtr->Chipset < CHIPS_CT65535)
6477 if (IS_STN(cPtr->PanelType)) {
6482 if (cPtr->Chipset == CHIPS_CT65548) {
6491 switch (cPtr->Chipset) {
6500 if (cPtr->PanelType & ChipsLCD)
6518 CHIPSPtr cPtr = CHIPSPTR(pScrn);
6524 if (IS_HiQV(cPtr)) {
6525 cPtr->writeXR(cPtr, 0x0E, 0x00);
6526 if (cPtr->Flags & ChipsDualChannelSupport) {
6527 tmp = cPtr->readFR(cPtr, 0x01); /* Disable pipeline */
6528 cPtr->writeFR(cPtr, 0x01, (tmp & 0xFC));
6529 cPtr->writeFR(cPtr, 0x02, 0x00); /* CRT/FP off */
6532 cPtr->writeXR(cPtr, 0x10, 0x00);
6533 cPtr->writeXR(cPtr, 0x11, 0x00);
6534 tmp = cPtr->readXR(cPtr, 0x0C) & ~0x50; /* WINgine stores MSB here */
6535 cPtr->writeXR(cPtr, 0x0C, tmp);
6536 cPtr->writeXR(cPtr, 0x15, 0x00); /* unprotect all registers */
6537 tmp = cPtr->readXR(cPtr, 0x14);
6538 cPtr->writeXR(cPtr, 0x14, tmp & ~0x20); /* enable vsync on ST01 */
6548 if ((cPtr->SyncResetIgn) && (!(cPtr->Flags & ChipsDualChannelSupport))) {
6557 VgaReg->MiscOutReg = inb(cPtr->PIOBase + 0x3CC);
6572 if (cPtr->Flags & ChipsDualChannelSupport) {
6574 cPtr->writeFR(cPtr, 0x01, ChipsReg->FR[0x01]);
6575 cPtr->writeFR(cPtr, 0x02, ChipsReg->FR[0x02]);
6584 if (IS_HiQV(cPtr)) {
6596 } else if (!IS_Wingine(cPtr))
6601 if (!cPtr->SyncResetIgn) {
6602 if (!IS_HiQV(cPtr)) {
6604 tmp = cPtr->readXR(cPtr, 0x0E);
6605 cPtr->writeXR(cPtr, 0x0E, tmp & 0x7F);
6610 if (!IS_HiQV(cPtr))
6611 cPtr->writeXR(cPtr, 0x0E, tmp);
6614 if (IS_HiQV(cPtr) && (ChipsReg->XR[0x09] & 0x1) == 0x1) {
6625 if (cPtr->Flags & ChipsDualChannelSupport) {
6626 cPtr->writeFR(cPtr, 0x01, ChipsReg->FR[0x01]);
6627 cPtr->writeFR(cPtr, 0x02, ChipsReg->FR[0x02]);
6636 CHIPSPtr cPtr = CHIPSPTR(pScrn);
6640 if (IS_HiQV(cPtr)) {
6643 if ((cPtr->readXR(cPtr, i)) != Regs->XR[i])
6644 cPtr->writeXR(cPtr, i, Regs->XR[i]);
6648 if ((cPtr->Flags & ChipsVideoSupport)) {
6650 cPtr->writeXR(cPtr, 0x4E, 0x04);
6651 if (cPtr->readXR(cPtr, 0x4F) != Regs->XR[0x4F])
6652 cPtr->writeXR(cPtr, 0x4F, Regs->XR[0x4F]);
6658 if ((cPtr->readXR(cPtr, i)) != Regs->XR[i])
6659 cPtr->writeXR(cPtr, i, Regs->XR[i]);
6664 tmp = cPtr->readXR(cPtr, 0xCE); /* Select Fixed MClk before */
6665 cPtr->writeXR(cPtr, 0xCE, tmp & 0x7F);
6666 if ((cPtr->readXR(cPtr, 0xCC)) != Regs->XR[0xCC])
6667 cPtr->writeXR(cPtr, 0xCC, Regs->XR[0xCC]);
6668 if ((cPtr->readXR(cPtr, 0xCD)) != Regs->XR[0xCD])
6669 cPtr->writeXR(cPtr, 0xCD, Regs->XR[0xCD]);
6670 if ((cPtr->readXR(cPtr, 0xCE)) != Regs->XR[0xCE])
6671 cPtr->writeXR(cPtr, 0xCE, Regs->XR[0xCE]);
6675 if ((cPtr->readXR(cPtr, i)) != Regs->XR[i])
6676 cPtr->writeXR(cPtr, i, Regs->XR[i]);
6681 if ((i == 0x01) && (cPtr->Chipset == CHIPS_CT69030)) {
6683 tmp = cPtr->readFR(cPtr, 0x01);
6684 cPtr->writeFR(cPtr, 0x01, ((Regs->FR[0x01] & 0xF0) |
6689 if ((i == 0x02) && (cPtr->Chipset == CHIPS_CT69030))
6693 if ((i == 0x03) && (cPtr->Chipset != CHIPS_CT69030)) {
6695 tmp = cPtr->readFR(cPtr, 0x03);
6696 cPtr->writeFR(cPtr, 0x03, ((Regs->FR[0x03] & 0xC3) |
6701 if ((i > 0x03) && (cPtr->Chipset != CHIPS_CT69030) &&
6702 (cPtr->SecondCrtc == TRUE))
6707 cPtr->writeFR(cPtr, i, Regs->FR[i] & 0xFE);
6710 if ((cPtr->readFR(cPtr, i)) != Regs->FR[i]) {
6711 cPtr->writeFR(cPtr, i, Regs->FR[i]);
6719 if ((cPtr->readMR(cPtr, i)) != Regs->MR[i])
6720 cPtr->writeMR(cPtr, i, Regs->MR[i]);
6731 if ((cPtr->readXR(cPtr, i)) != Regs->XR[i])
6732 cPtr->writeXR(cPtr, i, Regs->XR[i]);
6734 cPtr->writeXR(cPtr, 0x15, 0x00); /* unprotect just in case ... */
6737 if ((cPtr->readXR(cPtr, i)) != Regs->XR[i])
6738 cPtr->writeXR(cPtr, i, Regs->XR[i]);
6740 tmp = cPtr->readXR(cPtr, 0x54); /* restore the non clock bits */
6741 cPtr->writeXR(cPtr, 0x54, ((Regs->XR[0x54] & 0xF3) | (tmp & ~0xF3)));
6742 cPtr->writeXR(cPtr, 0x55, Regs->XR[0x55] & 0xFE); /* h-comp off */
6743 cPtr->writeXR(cPtr, 0x56, Regs->XR[0x56]);
6744 cPtr->writeXR(cPtr, 0x57, Regs->XR[0x57] & 0xFE); /* v-comp off */
6746 if ((cPtr->readXR(cPtr, i)) != Regs->XR[i])
6747 cPtr->writeXR(cPtr, i, Regs->XR[i]);
6752 if (IS_HiQV(cPtr)) {
6755 cPtr->readXR(cPtr, i));
6759 cPtr->readFR(cPtr, i));
6764 cPtr->readXR(cPtr, i));
6775 CHIPSPtr cPtr = CHIPSPTR(pScrn);
6778 if (IS_HiQV(cPtr)) {
6779 tmp = cPtr->readFR(cPtr, 0x48);
6780 cPtr->writeFR(cPtr, 0x48, (tmp & 0xFE) | (ctVerticalStretch & 0x01));
6781 tmp = cPtr->readFR(cPtr, 0x40);
6782 cPtr->writeFR(cPtr, 0x40, (tmp & 0xFE) | (ctHorizontalStretch & 0x01));
6784 tmp = cPtr->readXR(cPtr, 0x55);
6785 cPtr->writeXR(cPtr, 0x55, (tmp & 0xFE) | (ctHorizontalStretch & 0x01));
6786 tmp = cPtr->readXR(cPtr, 0x57);
6787 cPtr->writeXR(cPtr, 0x57, (tmp & 0xFE) | (ctVerticalStretch & 0x01));
6859 CHIPSPtr cPtr = CHIPSPTR(pScrn);
6863 if (cPtr->Flags & ChipsLinearSupport) {
6864 if (cPtr->UseMMIO) {
6865 if (IS_HiQV(cPtr)) {
6867 if (cPtr->pEnt->location.type == BUS_PCI)
6868 cPtr->MMIOBase = xf86MapPciMem(pScrn->scrnIndex,
6869 VIDMEM_MMIO_32BIT,cPtr->PciTag, cPtr->IOAddress,
6872 cPtr->MMIOBase = xf86MapVidMem(pScrn->scrnIndex,
6873 VIDMEM_MMIO_32BIT, cPtr->IOAddress, 0x20000L);
6877 void** result = (void**)&cPtr->MMIOBase;
6879 if (cPtr->pEnt->location.type == BUS_PCI) {
6880 err = pci_device_map_range(cPtr->PciInfo,
6881 cPtr->IOAddress,
6891 cPtr->IOAddress);
6902 if (cPtr->pEnt->location.type == BUS_PCI)
6903 cPtr->MMIOBase = xf86MapPciMem(pScrn->scrnIndex,
6904 VIDMEM_MMIO_32BIT, cPtr->PciTag, cPtr->IOAddress,
6907 cPtr->MMIOBase = xf86MapVidMem(pScrn->scrnIndex,
6908 VIDMEM_MMIO_32BIT, cPtr->IOAddress, 0x10000L);
6912 void** result = (void**)&cPtr->MMIOBase;
6914 if (cPtr->pEnt->location.type == BUS_PCI) {
6915 err = pci_device_map_range(cPtr->PciInfo,
6916 cPtr->IOAddress,
6926 cPtr->IOAddress);
6937 if (cPtr->MMIOBase == NULL)
6940 if (cPtr->FbMapSize) {
6941 unsigned long Addr = (unsigned long)cPtr->FbAddress;
6942 unsigned int Map = cPtr->FbMapSize;
6948 if ((cPtr->Flags & ChipsDualChannelSupport) &&
6952 if (cPtr->SecondCrtc == FALSE) {
6962 if (cPtr->pEnt->location.type == BUS_PCI)
6963 cPtr->FbBase = xf86MapPciMem(pScrn->scrnIndex,VIDMEM_FRAMEBUFFER,
6964 cPtr->PciTag, Addr, Map);
6967 cPtr->FbBase = xf86MapVidMem(pScrn->scrnIndex,VIDMEM_FRAMEBUFFER,
6970 result = (void**)&cPtr->FbBase;
6971 if (cPtr->pEnt->location.type == BUS_PCI) {
6972 err = pci_device_map_range(cPtr->PciInfo,
6991 if (cPtr->FbBase == NULL)
6994 if (cPtr->Flags & ChipsFullMMIOSupport) {
6996 cPtr->MMIOBaseVGA = xf86MapPciMem(pScrn->scrnIndex,
6997 VIDMEM_MMIO,cPtr->PciTag,
6998 cPtr->IOAddress, 0x2000L);
7000 cPtr->MMIOBaseVGA = cPtr->MMIOBase;
7010 if (cPtr->Flags & ChipsDualChannelSupport)
7013 cPtr->MMIOBasePipeB = xf86MapPciMem(pScrn->scrnIndex,
7014 VIDMEM_MMIO,cPtr->PciTag,
7015 cPtr->IOAddress + 0x800000, 0x2000L);
7017 void** result = (void**)&cPtr->MMIOBasePipeB;
7018 int err = pci_device_map_range(cPtr->PciInfo,
7019 cPtr->IOAddress + 0x800000,
7028 cPtr->MMIOBasePipeA = cPtr->MMIOBaseVGA;
7032 cPtr->FbBase = hwp->Base;
7046 CHIPSPtr cPtr = CHIPSPTR(pScrn);
7048 if (cPtr->Flags & ChipsLinearSupport) {
7049 if (IS_HiQV(cPtr)) {
7051 if (cPtr->MMIOBase)
7052 xf86UnMapVidMem(pScrn->scrnIndex, (pointer)cPtr->MMIOBase,
7054 if (cPtr->MMIOBasePipeB)
7055 xf86UnMapVidMem(pScrn->scrnIndex, (pointer)cPtr->MMIOBasePipeB,
7058 if (cPtr->MMIOBase)
7059 pci_device_unmap_range(cPtr->PciInfo, cPtr->MMIOBase, 0x20000);
7061 if (cPtr->MMIOBasePipeB)
7062 pci_device_unmap_range(cPtr->PciInfo, cPtr->MMIOBasePipeB, 0x2000);
7065 cPtr->MMIOBasePipeB = NULL;
7068 if (cPtr->MMIOBase)
7069 xf86UnMapVidMem(pScrn->scrnIndex, (pointer)cPtr->MMIOBase,
7072 if (cPtr->MMIOBase)
7073 pci_device_unmap_range(cPtr->PciInfo, cPtr->MMIOBase, 0x10000);
7076 cPtr->MMIOBase = NULL;
7078 xf86UnMapVidMem(pScrn->scrnIndex, (pointer)cPtr->FbBase,
7079 cPtr->FbMapSize);
7081 pci_device_unmap_range(cPtr->PciInfo, cPtr->FbBase, cPtr->FbMapSize);
7084 cPtr->FbBase = NULL;
7098 CHIPSPtr cPtr = CHIPSPTR(pScrn);
7103 if (cPtr->UseDualChannel) {
7110 if (!IS_HiQV(cPtr))
7111 cPtr->writeXR(cPtr, 0x15, 0x00);
7122 if (!cPtr->SyncResetIgn) {
7129 if (!cPtr->SyncResetIgn) {
7133 if ((cPtr->UseDualChannel) &&
7136 IOSS = cPtr->readIOSS(cPtr);
7137 MSS = cPtr->readMSS(cPtr);
7138 cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
7140 cPtr->writeMSS(cPtr, hwp, ((cPtr->storeMSS & MSS_MASK) | MSS_PIPE_B));
7143 if (!IS_HiQV(cPtr))
7144 cPtr->writeXR(cPtr, 0x15, 0x00);
7155 if (!cPtr->SyncResetIgn) {
7162 if (!cPtr->SyncResetIgn) {
7166 cPtr->writeIOSS(cPtr, IOSS);
7167 cPtr->writeMSS(cPtr, hwp, MSS);
7176 CHIPSPtr cPtr = CHIPSPTR(pScrn);
7181 if (!IS_HiQV(cPtr)) {
7183 cPtr->writeXR(cPtr, 0x15, cPtr->SuspendHack.xr15);
7184 tmp = cPtr->readXR(cPtr, 0x02);
7185 cPtr->writeXR(cPtr, 0x02, (tmp & ~0x18) | cPtr->SuspendHack.xr02);
7186 tmp = cPtr->readXR(cPtr, 0x14);
7187 cPtr->writeXR(cPtr, 0x14, (tmp & ~0x20) | cPtr->SuspendHack.xr14);
7190 if (cPtr->Chipset > CHIPS_CT65540) {
7191 tmp = cPtr->readXR(cPtr, 0x03);
7192 cPtr->writeXR(cPtr, 0x03, (tmp & ~0x0A) | cPtr->SuspendHack.xr03);
7201 CHIPSPtr cPtr = CHIPSPTR(pScrn);
7204 if (!IS_HiQV(cPtr)) {
7206 cPtr->writeXR(cPtr, 0x15, 0x00);
7207 tmp = cPtr->readXR(cPtr, 0x02);
7208 cPtr->writeXR(cPtr, 0x02, (tmp & ~0x18));
7209 tmp = cPtr->readXR(cPtr, 0x14);
7210 cPtr->writeXR(cPtr, 0x14, (tmp & ~0x20));
7212 if (cPtr->Chipset > CHIPS_CT65540) {
7213 cPtr->writeXR(cPtr, 0x03, cPtr->SuspendHack.xr03 | 0x0A);
7220 chipsHWCursorOn(CHIPSPtr cPtr, ScrnInfoPtr pScrn)
7223 if (cPtr->HWCursorShown) {
7224 if (IS_HiQV(cPtr)) {
7225 cPtr->writeXR(cPtr, 0xA0, cPtr->HWCursorContents & 0xFF);
7226 if (cPtr->UseDualChannel &&
7229 IOSS = cPtr->readIOSS(cPtr);
7230 MSS = cPtr->readMSS(cPtr);
7231 cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |
7233 cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &
7235 cPtr->writeXR(cPtr, 0xA0, cPtr->HWCursorContents & 0xFF);
7236 cPtr->writeIOSS(cPtr, IOSS);
7237 cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), MSS);
7241 if (cPtr->UseMMIO) {
7242 MMIOmeml(DR(0x8)) = cPtr->HWCursorContents;
7244 outl(cPtr->PIOBase + DR(0x8), cPtr->HWCursorContents);
7251 chipsHWCursorOff(CHIPSPtr cPtr, ScrnInfoPtr pScrn)
7254 if (cPtr->HWCursorShown) {
7255 if (IS_HiQV(cPtr)) {
7256 cPtr->HWCursorContents = cPtr->readXR(cPtr, 0xA0);
7257 cPtr->writeXR(cPtr, 0xA0, cPtr->HWCursorContents & 0xF8);
7260 if (cPtr->UseMMIO) {
7261 cPtr->HWCursorContents = MMIOmeml(DR(0x8));
7264 MMIOmeml(DR(0x8)) = cPtr->HWCursorContents & 0xFFFE;
7266 cPtr->HWCursorContents = inl(cPtr->PIOBase + DR(0x8));
7267 outw(cPtr->PIOBase + DR(0x8), cPtr->HWCursorContents & 0xFFFE);
7276 CHIPSPtr cPtr = CHIPSPTR(pScrn);
7281 if (!IS_HiQV(cPtr))
7282 cPtr->writeXR(cPtr, 0x15, 0x00);
7284 hwp->writeMiscOut(hwp, (tmp & 0xFE) | cPtr->SuspendHack.vgaIOBaseFlag);
7311 CHIPSPtr cPtr = CHIPSPTR(pScrn);
7320 if (cPtr->Flags & ChipsDualChannelSupport) {
7321 IOSS = cPtr->readIOSS(cPtr);
7322 MSS = cPtr->readMSS(cPtr);
7323 tmpfr02 = cPtr->readFR(cPtr,0x02);
7324 cPtr->writeFR(cPtr, 0x02, (tmpfr02 & 0xCF)); /* CRT/FP off */
7326 cPtr->writeIOSS(cPtr, ((IOSS & IOSS_MASK) | IOSS_PIPE_A));
7327 cPtr->writeMSS(cPtr, hwp, ((MSS & MSS_MASK) | MSS_PIPE_A));
7328 tmpfr01a = cPtr->readFR(cPtr,0x01);
7330 cPtr->writeFR(cPtr, 0x01, ((tmpfr01a & 0xFC) | 0x1));
7331 cPtr->writeIOSS(cPtr, ((IOSS & IOSS_MASK) | IOSS_PIPE_B));
7332 cPtr->writeMSS(cPtr, hwp, ((MSS & MSS_MASK) | MSS_PIPE_B));
7333 tmpfr01b = cPtr->readFR(cPtr,0x01);
7335 cPtr->writeFR(cPtr, 0x01, ((tmpfr01b & 0xFC) | 0x1));
7336 cPtr->writeIOSS(cPtr, IOSS);
7337 cPtr->writeMSS(cPtr, hwp, MSS);
7338 cPtr->writeFR(cPtr, 0x02, (tmpfr02 & 0xCF) | 0x10); /* CRT on/FP off*/
7349 if (!IS_HiQV(cPtr)) {
7350 xr1 = cPtr->readXR(cPtr, 0x06);
7351 xr2 = cPtr->readXR(cPtr, 0x1F);
7352 cPtr->writeXR(cPtr, 0x06, xr1 & 0xF1); /* turn on dac */
7353 cPtr->writeXR(cPtr, 0x1F, xr2 & 0x7F); /* enable comp */
7355 xr1 = cPtr->readXR(cPtr, 0x81);
7356 xr2 = cPtr->readXR(cPtr, 0xD0);
7357 cPtr->writeXR(cPtr, 0x81,(xr1 & 0xF0));
7358 cPtr->writeXR(cPtr, 0xD0,(xr2 | 0x03));
7381 if (!IS_HiQV(cPtr)) {
7382 cPtr->writeXR(cPtr,0x06,xr1);
7383 cPtr->writeXR(cPtr,0x1F,xr2);
7385 cPtr->writeXR(cPtr,0x81,xr1);
7386 cPtr->writeXR(cPtr,0xD0,xr2);
7389 if (cPtr->Flags & ChipsDualChannelSupport) {
7390 cPtr->writeIOSS(cPtr, ((IOSS & IOSS_MASK) | IOSS_PIPE_A));
7391 cPtr->writeMSS(cPtr, hwp, ((MSS & MSS_MASK) | MSS_PIPE_A));
7392 cPtr->writeFR(cPtr, 0x01, tmpfr01a);
7393 cPtr->writeIOSS(cPtr, ((IOSS & IOSS_MASK) | IOSS_PIPE_B));
7394 cPtr->writeMSS(cPtr, hwp, ((MSS & MSS_MASK) | MSS_PIPE_B));
7395 cPtr->writeFR(cPtr, 0x01, tmpfr01b);
7397 cPtr->writeIOSS(cPtr, IOSS);
7398 cPtr->writeMSS(cPtr, hwp, MSS);
7399 cPtr->writeFR(cPtr, 0x02, tmpfr02);
7424 chipsSetPanelType(CHIPSPtr cPtr)
7428 if (IS_HiQV(cPtr)) {
7429 if (cPtr->Chipset == CHIPS_CT69030) {
7430 tmp = cPtr->readFR(cPtr, 0x00);
7434 tmp = cPtr->readFR(cPtr, 0x02);
7436 cPtr->PanelType |= ChipsCRT;
7438 cPtr->PanelType |= ChipsLCD | ChipsLCDProbed;
7440 cPtr->PanelType |= ChipsCRT;
7447 tmp = cPtr->readFR(cPtr, 0x01);
7449 cPtr->PanelType |= ChipsLCD | ChipsLCDProbed;
7451 tmp = cPtr->readXR(cPtr,0xD0);
7453 cPtr->PanelType |= ChipsCRT;
7457 tmp = cPtr->readXR(cPtr, 0x51);
7462 cPtr->PanelType |= ChipsLCD | ChipsLCDProbed;
7464 if ((cPtr->readXR(cPtr, 0x06)) & 0x02) {
7465 cPtr->PanelType |= ChipsCRT;
7475 CHIPSPtr cPtr = CHIPSPTR(pScrn);
7477 pScreen->BlockHandler = cPtr->BlockHandler;
7481 if(cPtr->VideoTimerCallback) {
7483 (*cPtr->VideoTimerCallback)(pScrn, currentTime.milliseconds);