Lines Matching refs:ChipsNew
5301 CHIPSRegPtr ChipsNew;
5305 ChipsNew = &cPtr->ModeReg;
5326 if (!chipsClockFind(pScrn, mode, mode->ClockIndex, &ChipsNew->Clock)) {
5335 if (((ChipsNew->Clock.FPClock + ChipsNew->Clock.Clock) *
5353 ChipsNew->XR[i] = cPtr->readXR(cPtr, i);
5356 ChipsNew->FR[i] = cPtr->readFR(cPtr, i);
5359 ChipsNew->MR[i] = cPtr->readMR(cPtr, i);
5362 ChipsNew->CR[i] = hwp->readCrtc(hwp, i);
5366 * Here all of the other fields of 'ChipsNew' get filled in, to
5395 ChipsNew->CR[0x41] = (tmp >> 8) & 0x0F;
5399 ChipsNew->XR[0x0A] |= 0x1;
5402 ChipsNew->XR[0x0A] &= 0xCF;
5405 ChipsNew->XR[0x0A] |= 0x10;
5408 ChipsNew->XR[0x09] |= 0x1; /* Enable extended CRT registers */
5409 ChipsNew->XR[0x0E] = 0; /* Single map */
5410 ChipsNew->XR[0x40] |= 0x2; /* Don't wrap at 256kb */
5411 ChipsNew->XR[0x81] &= 0xF8;
5413 ChipsNew->XR[0x40] |= 0x1; /* High Resolution. XR40[1] reserved? */
5414 ChipsNew->XR[0x81] |= 0x2; /* 256 Color Video */
5416 ChipsNew->XR[0x80] |= 0x10; /* Enable cursor output on P0 and P1 */
5419 ChipsNew->XR[0x80] |= 0x80;
5421 ChipsNew->XR[0x80] &= ~0x80;
5426 ChipsNew->XR[0xCC] = cPtr->MemClock.xrCC;
5427 ChipsNew->XR[0xCD] = cPtr->MemClock.xrCD;
5428 ChipsNew->XR[0xCE] = cPtr->MemClock.xrCE;
5433 ChipsNew->FR[0x01] &= 0xFC;
5435 ChipsNew->FR[0x01] |= 0x02;
5437 ChipsNew->FR[0x01] |= 0x01;
5438 ChipsNew->FR[0x02] &= 0xCC;
5440 ChipsNew->FR[0x02] |= 0x01; /* Set DAC to pipe B */
5442 ChipsNew->FR[0x02] &= 0xFE; /* Set DAC to pipe A */
5445 ChipsNew->FR[0x02] |= 0x20; /* Enable the LCD output */
5447 ChipsNew->FR[0x02] |= 0x10; /* Enable the CRT output */
5452 ChipsNew->XR[0x0A] |= 0x02; /* Linear Addressing Mode */
5453 ChipsNew->XR[0x20] = 0x0; /*BitBLT Draw Mode for 8 */
5454 ChipsNew->XR[0x05] =
5456 ChipsNew->XR[0x06] =
5474 ChipsNew->FR[0x20] = lcdHDisplay & 0xFF;
5475 ChipsNew->FR[0x21] = lcdHRetraceStart & 0xFF;
5476 ChipsNew->FR[0x25] = ((lcdHRetraceStart & 0xF00) >> 4) |
5478 ChipsNew->FR[0x22] = lcdHRetraceEnd & 0x1F;
5479 ChipsNew->FR[0x23] = lcdHTotal & 0xFF;
5480 ChipsNew->FR[0x24] = (lcdHSyncStart >> 3) & 0xFF;
5481 ChipsNew->FR[0x26] = (ChipsNew->FR[0x26] & ~0x1F)
5484 ChipsNew->FR[0x27] &= 0x7F;
5486 ChipsNew->FR[0x30] = lcdVDisplay & 0xFF;
5487 ChipsNew->FR[0x31] = lcdVRetraceStart & 0xFF;
5488 ChipsNew->FR[0x35] = ((lcdVRetraceStart & 0xF00) >> 4)
5490 ChipsNew->FR[0x32] = lcdVRetraceEnd & 0x0F;
5491 ChipsNew->FR[0x33] = lcdVTotal & 0xFF;
5492 ChipsNew->FR[0x34] = (lcdVTotal - lcdVRetraceStart) & 0xFF;
5493 ChipsNew->FR[0x36] = ((lcdVTotal & 0xF00) >> 8) |
5495 ChipsNew->FR[0x37] |= 0x80;
5499 ChipsNew->CR[0x30] = ((mode->CrtcVTotal - 2) & 0xF00) >> 8;
5500 ChipsNew->CR[0x31] = ((mode->CrtcVDisplay - 1) & 0xF00) >> 8;
5501 ChipsNew->CR[0x32] = (mode->CrtcVSyncStart & 0xF00) >> 8;
5502 ChipsNew->CR[0x33] = (mode->CrtcVBlankStart & 0xF00) >> 8;
5505 ChipsNew->CR[0x38] = (((mode->CrtcHTotal >> 3) - 5) & 0x100) >> 8;
5506 ChipsNew->CR[0x3C] = vgaHWHBlankKGA(mode, ChipsStd, 8, 0) << 6;
5511 ChipsNew->CR[0x40] |= 0x80;
5516 ChipsNew->FR[0x40] &= 0xDF; /* Disable Horizontal stretching */
5517 ChipsNew->FR[0x48] &= 0xFB; /* Disable vertical stretching */
5518 ChipsNew->XR[0xA0] = 0x10; /* Disable cursor stretching */
5520 ChipsNew->FR[0x40] |= 0x21; /* Enable Horizontal stretching */
5521 ChipsNew->FR[0x48] |= 0x05; /* Enable vertical stretching */
5522 ChipsNew->XR[0xA0] = 0x70; /* Enable cursor stretching */
5536 ChipsNew->FR[0x40] |= 0x3; /* Enable Horizontal centering */
5537 ChipsNew->FR[0x48] |= 0x3; /* Enable Vertical centering */
5539 ChipsNew->FR[0x40] &= 0xFD; /* Disable Horizontal centering */
5540 ChipsNew->FR[0x48] &= 0xFD; /* Disable Vertical centering */
5545 ChipsNew->XR[0x82] |=0x02;
5548 ChipsNew->XR[0xE2] = chipsVideoMode((pScrn->depth), (cPtr->PanelType & ChipsLCD) ?
5552 ErrorF("VESA Mode: %Xh\n", ChipsNew->XR[0xE2]);
5560 ChipsNew->FR[0x08] &= 0xBF; /* Alt. CRT Hsync positive */
5562 ChipsNew->FR[0x08] |= 0x40; /* Alt. CRT Hsync negative */
5566 ChipsNew->FR[0x08] &= 0x7F; /* Alt. CRT Vsync positive */
5568 ChipsNew->FR[0x08] |= 0x80; /* Alt. CRT Vsync negative */
5572 ChipsNew->FR[0x0B] |= 0x20;
5574 ChipsNew->FR[0x08] &= 0x7F; /* Alt. CRT Vsync positive */
5575 ChipsNew->FR[0x08] &= 0xBF; /* Alt. CRT Hsync positive */
5579 ChipsNew->FR[0x08] |= 0x80; /* Alt. CRT Vsync negative */
5580 ChipsNew->FR[0x08] |= 0x40; /* Alt. CRT Hsync negative */
5587 ChipsNew->XR[0x81] = (ChipsNew->XR[0x81] & 0xF0) | 0x4;
5589 ChipsNew->XR[0x82] |= 0x0C;
5591 ChipsNew->FR[0x10] |= 0x0C; /*Colour Panel */
5592 ChipsNew->XR[0x20] = 0x10; /*BitBLT Draw Mode for 16 bpp */
5594 ChipsNew->XR[0x81] |= 0x01; /*16bpp */
5596 ChipsNew->XR[0x81] = (ChipsNew->XR[0x81] & 0xF0) | 0x6;
5598 ChipsNew->XR[0x82] |= 0x0C;
5600 ChipsNew->XR[0x20] = 0x20; /*BitBLT Draw Mode for 24 bpp */
5602 ChipsNew->XR[0x81] = (ChipsNew->XR[0x81] & 0xF0) | 0x7;
5604 ChipsNew->XR[0x82] |= 0x0C;
5606 ChipsNew->XR[0x20] = 0x10; /*BitBLT Mode for 16bpp used at 32bpp */
5612 ChipsNew->CR[0x70] = 0x80 /* set interlace */
5624 ChipsNew->CR[0x31] = ((mode->CrtcVDisplay - 1) & 0xF00) >> 8;
5626 ChipsNew->CR[0x70] &= ~0x80; /* unset interlace */
5637 ChipsNew->CR[0x72] = (mode->CrtcHTotal >> 1) >> 3;/* First horizontal
5639 ChipsNew->CR[0x73] = mode->CrtcHTotal >> 3; /* Second pulse */
5640 ChipsNew->CR[0x74] = (((mode->HSyncEnd - mode->HSyncStart) >> 3) - 1)
5644 ChipsNew->CR[0x71] = 0xA0; /* PAL support with blanking delay */
5646 ChipsNew->CR[0x71] = 0x20; /* NTSC support with blanking delay */
5658 ChipsNew->FR[0x11] &= ~0x03; /* FRC clear */
5659 ChipsNew->FR[0x11] &= ~0x8C; /* Dither clear */
5660 ChipsNew->FR[0x11] |= 0x01; /* 16 frame FRC */
5661 ChipsNew->FR[0x11] |= 0x84; /* Dither */
5664 ChipsNew->FR[0x73] &= 0x4F; /* Clear TMED */
5665 ChipsNew->FR[0x73] |= 0x80; /* Enable TMED */
5666 ChipsNew->FR[0x73] |= 0x30; /* TMED 256 Shades of RGB */
5669 ChipsNew->FR[0x12] |= 0x4; /* rid of line in DSTN screens */
5680 cPtr->OverlaySkewX = (((ChipsNew->FR[0x23] & 0xFF)
5681 - (ChipsNew->FR[0x20] & 0xFF) + 3) << 3)
5683 cPtr->OverlaySkewY = (ChipsNew->FR[0x33]
5684 + ((ChipsNew->FR[0x36] & 0xF) << 8)
5685 - (ChipsNew->FR[0x31] & 0xF0)
5686 - (ChipsNew->FR[0x32] & 0x0F)
5687 - ((ChipsNew->FR[0x35] & 0xF0) << 4));
5737 ChipsNew->XR[0xD0] &= 0x0f;
5741 ChipsNew->XR[0xD0] |= 0x10; /* Force the Multimedia engine on */
5744 ChipsNew->XR[0x4F] = 0x2A; /* SAR04 >352 pixel overlay width */
5746 ChipsNew->MR[0x3C] &= 0x18; /* Ensure that the overlay is off */
5760 ChipsNew->FR[0x01] &= ~0x03;
5762 ChipsNew->FR[0x01] |= 0x02;
5764 ChipsNew->FR[0x01] |= 0x01;
5777 chipsRestore(pScrn, ChipsStd, ChipsNew, FALSE);
5785 tmpfr01 = ChipsNew->FR[0x01];
5786 ChipsNew->FR[0x01] &= 0xFC;
5788 ChipsNew->FR[0x01] |= 0x01;
5789 chipsRestore(pScrn, ChipsStd, ChipsNew, FALSE);
5790 ChipsNew->FR[0x01] = tmpfr01;
5794 chipsRestore(pScrn, ChipsStd, ChipsNew, FALSE);
5809 CHIPSRegPtr ChipsNew;
5813 ChipsNew = &cPtr->ModeReg;
5860 if (!chipsClockFind(pScrn, mode, mode->ClockIndex, &ChipsNew->Clock)) {
5867 ChipsNew->XR[i] = cPtr->readXR(cPtr, i);
5896 ChipsNew->XR[0x0D] = (tmp & 0x80) >> 5;
5898 ChipsNew->XR[0x04] |= 4; /* enable addr counter bits 16-17 */
5903 ChipsNew->XR[0x0B] |= 0x07; /* extended mode, dual pages enabled */
5904 ChipsNew->XR[0x0B] &= ~0x10; /* linear mode off */
5914 ChipsNew->XR[0x10] = 0; /* XR10: Single/low map */
5915 ChipsNew->XR[0x11] = 0; /* XR11: High map */
5916 ChipsNew->XR[0x0C] &= ~0x50; /* MSB for XR10 & XR11 */
5918 ChipsNew->XR[0x28] |= 0x10; /* 256-color video */
5920 ChipsNew->XR[0x28] &= 0xEF; /* 16-color video */
5924 ChipsNew->XR[0x17] = ((((mode->CrtcHTotal >> 3) - 5) & 0x100) >> 8)
5932 ChipsNew->XR[0x16] = (((mode->CrtcVTotal -2) & 0x400) >> 10 )
5938 ChipsNew->XR[0x2B] = chipsVideoMode(pScrn->depth, mode->CrtcHDisplay, mode->CrtcVDisplay);
5940 ErrorF("VESA Mode: %Xh\n", ChipsNew->XR[0x2B]);
5946 ChipsNew->XR[0x0B] &= 0xFD; /* dual page clear */
5947 ChipsNew->XR[0x0B] |= 0x10; /* linear mode on */
5949 ChipsNew->XR[0x08] =
5951 ChipsNew->XR[0x09] =
5955 ChipsNew->XR[0x40] = 0x01; /*BitBLT Draw Mode for 8 and 24 bpp */
5959 ChipsNew->XR[0x52] |= 0x01; /* Refresh count */
5960 ChipsNew->XR[0x0F] &= 0xEF; /* not Hi-/True-Colour */
5961 ChipsNew->XR[0x02] &= 0xE7; /* Attr. Cont. default access */
5963 ChipsNew->XR[0x06] &= 0xF3; /* bpp clear */
5992 ChipsNew->XR[0x06] |= 0xC4; /*15 or 16 bpp colour */
5993 ChipsNew->XR[0x0F] |= 0x10; /*Hi-/True-Colour */
5994 ChipsNew->XR[0x40] = 0x02; /*BitBLT Draw Mode for 16 bpp */
5996 ChipsNew->XR[0x06] |= 0x08; /*16bpp */
5998 ChipsNew->XR[0x06] |= 0xC8; /*24 bpp colour */
5999 ChipsNew->XR[0x0F] |= 0x10; /*Hi-/True-Colour */
6004 ChipsNew->XR[0x28] |= 0x20; /* set interlace */
6008 ChipsNew->XR[0x19] = tmp & 0xFF;
6009 ChipsNew->XR[0x17] |= ((tmp & 0x100) >> 1); /* overflow */
6010 ChipsNew->XR[0x0F] &= ~0x40; /* set SW-Flag */
6012 ChipsNew->XR[0x28] &= ~0x20; /* unset interlace */
6013 ChipsNew->XR[0x0F] |= 0x40; /* set SW-Flag */
6018 chipsRestore(pScrn, ChipsStd, ChipsNew, FALSE);
6036 CHIPSRegPtr ChipsNew;
6040 ChipsNew = &cPtr->ModeReg;
6102 if (!chipsClockFind(pScrn, mode, mode->ClockIndex, &ChipsNew->Clock)) {
6109 ChipsNew->XR[i] = cPtr->readXR(cPtr, i);
6133 ChipsNew->XR[0x1E] = ChipsStd->CRTC[0x13]; /* alternate offset */
6139 ChipsNew->XR[0x0D] = (tmp & 0x01) | ((tmp << 1) & 0x02) ;
6141 ChipsNew->XR[0x04] |= 4; /* enable addr counter bits 16-17 */
6146 ChipsNew->XR[0x0B] |= 0x07; /* extended mode, dual pages enabled */
6147 ChipsNew->XR[0x0B] &= ~0x10; /* linear mode off */
6157 ChipsNew->XR[0x10] = 0; /* XR10: Single/low map */
6158 ChipsNew->XR[0x11] = 0; /* XR11: High map */
6160 ChipsNew->XR[0x28] |= 0x10; /* 256-color video */
6162 ChipsNew->XR[0x28] &= 0xEF; /* 16-color video */
6167 ChipsNew->XR[0x17] = ((((mode->CrtcHTotal >> 3) - 5) & 0x100) >> 8)
6174 ChipsNew->XR[0x16] = (((mode->CrtcVTotal -2) & 0x400) >> 10 )
6230 ChipsNew->XR[0x17] = (((lcdHTotal) & 0x100) >> 8)
6235 ChipsNew->XR[0x19] = lcdHRetraceStart & 0xFF;
6236 ChipsNew->XR[0x1A] = lcdHRetraceEnd & 0x1F;
6242 ChipsNew->XR[0x1B] = lcdHTotal & 0xFF;
6250 ChipsNew->XR[0x1C] = lcdHDisplay & 0xFF;
6255 ChipsNew->XR[0x21] = lcdHRetraceStart & 0xFF;
6256 ChipsNew->XR[0x22] = lcdHRetraceEnd & 0x1F;
6257 ChipsNew->XR[0x23] = lcdHTotal & 0xFF;
6265 ChipsNew->XR[0x64] = lcdVTotal & 0xFF;
6266 ChipsNew->XR[0x66] = lcdVRetraceStart & 0xFF;
6267 ChipsNew->XR[0x67] = lcdVRetraceEnd & 0x0F;
6268 ChipsNew->XR[0x68] = lcdVDisplay & 0xFF;
6269 ChipsNew->XR[0x65] = ((lcdVTotal & 0x100) >> 8)
6285 tmp = ((cPtr->PanelType & ChipsDD) && !(ChipsNew->XR[0x6F] & 0x02))
6296 if ((unsigned)ChipsNew->XR[0x2C] < ((cPtr->PanelSize.VTotal -
6298 ChipsNew->XR[0x2C]))
6299 ChipsNew->XR[0x2F] |= 0x80; /* turn FLM delay off */
6300 ChipsNew->XR[0x2C] = lcdVTotal - lcdVRetraceStart - tmp;
6301 /*ChipsNew->XR[0x2D] = (HSyncStart >> (3 - tmp)) & 0xFF;*/
6302 ChipsNew->XR[0x2D] = (HDisplay >> (3 - tmp)) & 0xFF;
6303 ChipsNew->XR[0x2F] = (ChipsNew->XR[0x2F] & 0xDF)
6309 ChipsNew->XR[0x51] |= 0x40; /* enable FP compensation */
6310 ChipsNew->XR[0x55] |= 0x01; /* enable horiz. compensation */
6311 ChipsNew->XR[0x57] |= 0x01; /* enable horiz. compensation */
6315 ChipsNew->XR[0x55] |= 0x02; /* enable auto h-centering */
6317 ChipsNew->XR[0x55] &= 0xFD; /* disable auto h-centering */
6319 ChipsNew->XR[0x56] = (lcdHDisplay - CrtcHDisplay) >> 1;
6322 ChipsNew->XR[0x55] &= 0xFD; /* disable h-centering */
6323 ChipsNew->XR[0x56] = 0;
6325 ChipsNew->XR[0x57] = 0x03; /* enable v-comp disable v-stretch */
6328 ChipsNew->XR[0x55] |= 0x20; /* enable h-comp disable h-double*/
6329 ChipsNew->XR[0x57] |= 0x60; /* Enable vertical stretching */
6346 ChipsNew->XR[0x5A] = tmp > 0x0F ? 0 : (unsigned char)tmp;
6348 ChipsNew->XR[0x55] &= 0xDF; /* disable h-comp, h-double */
6349 ChipsNew->XR[0x57] &= 0x9F; /* disable vertical stretching */
6355 ChipsNew->XR[0x2B] = chipsVideoMode(pScrn->depth, (cPtr->PanelType & ChipsLCD) ?
6358 ErrorF("VESA Mode: %Xh\n", ChipsNew->XR[0x2B]);
6364 ChipsNew->XR[0x0B] &= 0xFD; /* dual page clear */
6365 ChipsNew->XR[0x0B] |= 0x10; /* linear mode on */
6367 ChipsNew->XR[0x08] = (unsigned char)(cPtr->FbAddress >> 17);
6369 ChipsNew->XR[0x08] = (unsigned char)(cPtr->FbAddress >> 20);
6375 ChipsNew->XR[0x04] &= ~0x40; /* A19 sceme */
6377 ChipsNew->XR[0x04] |= 0x40; /* MEMR/MEMW sceme */
6381 ChipsNew->XR[0x03] |= 0x08; /* High bandwidth on 65548 */
6382 ChipsNew->XR[0x40] = 0x01; /*BitBLT Draw Mode for 8 and 24 bpp */
6386 ChipsNew->XR[0x52] |= 0x01; /* Refresh count */
6387 ChipsNew->XR[0x0F] &= 0xEF; /* not Hi-/True-Colour */
6388 ChipsNew->XR[0x02] |= 0x01; /* 16bit CPU Memory Access */
6389 ChipsNew->XR[0x02] &= 0xE3; /* Attr. Cont. default access */
6391 ChipsNew->XR[0x06] &= 0xF3; /* bpp clear */
6395 ChipsNew->XR[0x03] |= 0x40; /*PCI burst */
6402 ChipsNew->XR[0x55] &= 0xBF; /* CRT Hsync positive */
6404 ChipsNew->XR[0x55] |= 0x40; /* CRT Hsync negative */
6409 ChipsNew->XR[0x55] &= 0x7F; /* CRT Vsync positive */
6411 ChipsNew->XR[0x55] |= 0x80; /* CRT Vsync negative */
6443 ChipsNew->XR[0x06] |= 0xC4; /*15 or 16 bpp colour */
6444 ChipsNew->XR[0x0F] |= 0x10; /*Hi-/True-Colour */
6445 ChipsNew->XR[0x40] = 0x02; /*BitBLT Draw Mode for 16 bpp */
6447 ChipsNew->XR[0x06] |= 0x08; /*16bpp */
6449 ChipsNew->XR[0x06] |= 0xC8; /*24 bpp colour */
6450 ChipsNew->XR[0x0F] |= 0x10; /*Hi-/True-Colour */
6452 ChipsNew->XR[0x50] &= 0x7F; /*18 bit TFT data width */
6454 ChipsNew->XR[0x50] |= 0x80; /*24 bit TFT data width */
6461 ChipsNew->XR[0x28] |= 0x20; /* set interlace */
6466 ChipsNew->XR[0x19] = tmp & 0xFF;
6468 ChipsNew->XR[0x29] = tmp & 0xFF;
6469 ChipsNew->XR[0x0F] &= ~0x40; /* set SW-Flag */
6471 ChipsNew->XR[0x28] &= ~0x20; /* unset interlace */
6472 ChipsNew->XR[0x0F] |= 0x40; /* set SW-Flag */
6478 ChipsNew->XR[0x50] &= ~0x03; /* FRC clear */
6479 ChipsNew->XR[0x50] |= 0x01; /* 16 frame FRC */
6480 ChipsNew->XR[0x50] &= ~0x0C; /* Dither clear */
6481 ChipsNew->XR[0x50] |= 0x08; /* Dither all modes */
6483 ChipsNew->XR[0x03] |= 0x20; /* CRT I/F priority */
6484 ChipsNew->XR[0x04] |= 0x10; /* RAS precharge 65548 */
6493 ChipsNew->XR[0x03] |= 0x10; /* do not hold off CPU for palette acc*/
6496 ChipsNew->XR[0x05] |= 0x80; /* EDO RAM enable */
6501 ChipsNew->XR[0x51] |= 0x04;
6503 ChipsNew->XR[0x51] &= ~0x04;
6507 chipsRestore(pScrn, ChipsStd, ChipsNew, FALSE);