Lines Matching defs:pCir
107 static void AlpSetClock(CirPtr pCir, vgaHWPtr hwp, int freq);
253 CirPtr pCir = CIRPTR(pScrn);
259 pCir->FbMapSize = 1024*1024; /* XX temp */
260 if (!pCir->IoMapSize)
261 pCir->IoMapSize = 0x4000; /* 16K for moment */
262 if (!CirMapMem(pCir, pScrn->scrnIndex))
267 switch (pCir->Chipset)
272 if (pCir->UseMMIO)
273 vgaHWSetMmioFuncs(hwp, pCir->IOBase, -0x3C0);
276 if (pCir->chip.alp->sr0f != (CARD32)-1) {
278 hwp->writeSeq(hwp, 0x0F, pCir->chip.alp->sr0f);
281 pCir->chip.alp->sr0f = hwp->readSeq(hwp, 0x0F);
284 (unsigned int)pCir->chip.alp->sr0f);
286 switch (pCir->Chipset) {
289 switch (pCir->chip.alp->sr0f & 0x18) {
305 switch (pCir->chip.alp->sr0f & 0x18) {
311 if (pCir->chip.alp->sr0f & 0x80)
319 if (pCir->chip.alp->sr17 != (CARD32)-1) {
321 hwp->writeSeq(hwp, 0x17, pCir->chip.alp->sr17);
324 pCir->chip.alp->sr17 = hwp->readSeq(hwp, 0x17);
327 (unsigned int)pCir->chip.alp->sr17);
329 if ((pCir->chip.alp->sr0f & 0x18) == 0x18) {
330 if (pCir->chip.alp->sr0f & 0x80) {
331 if (pCir->chip.alp->sr17 & 0x80)
333 else if (pCir->chip.alp->sr17 & 0x02)
338 if ((pCir->chip.alp->sr17 & 80) == 0)
345 if (pCir->chip.alp->sr17 != (CARD32)-1) {
347 hwp->writeSeq(hwp, 0x17, pCir->chip.alp->sr17);
350 pCir->chip.alp->sr17 = hwp->readSeq(hwp, 0x17);
353 (unsigned int)pCir->chip.alp->sr17);
355 if ((pCir->chip.alp->sr0f & 0x18) == 0x18) { /* 2 or 4 MB */
357 if (pCir->chip.alp->sr0f & 0x80) /* Second bank enable */
360 if (pCir->chip.alp->sr17 & 0x80)
366 switch (pCir->chip.alp->sr0f & 0x90) {
383 if (!CirUnmapMem(pCir, pScrn->scrnIndex))
404 CirPtr pCir = CIRPTR(pScrn);
420 switch (pCir->Chipset) {
433 if ((accelWidths[i] % pCir->Rounding == 0)
453 CirPtr pCir;
491 pCir = CIRPTR(pScrn);
492 pCir->pScrn = pScrn;
495 pCir->PIOReg = hwp->PIOOffset + 0x3CE;
497 pCir->PIOReg = 0x3CE;
501 pCir->pEnt = xf86GetEntityInfo(pScrn->entityList[0]);
502 if (pCir->pEnt->location.type != BUS_PCI) {
503 free(pCir->pEnt);
507 pCir->Chipset = pCir->pEnt->chipset;
509 pCir->PciInfo = xf86GetPciInfoForEntity(pCir->pEnt->index);
511 pCir->PciTag = pciTag(PCI_DEV_BUS(pCir->PciInfo),
512 PCI_DEV_DEV(pCir->PciInfo),
513 PCI_DEV_FUNC(pCir->PciInfo));
522 pInt = xf86InitInt10(pCir->pEnt->index);
529 PCI_WRITE_LONG(pCir->PciInfo, PCI_REGION_BASE(pCir->PciInfo, 0, REGION_MEM), 0x10);
530 PCI_WRITE_LONG(pCir->PciInfo, PCI_REGION_BASE(pCir->PciInfo, 1, REGION_MEM), 0x14);
538 if (pCir->Chipset == PCI_CHIP_GD5480 || pCir->Chipset ==PCI_CHIP_GD7548)
596 if (!(pCir->Options = malloc(sizeof(CirOptions))))
598 memcpy(pCir->Options, CirOptions, sizeof(CirOptions));
599 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, pCir->Options);
601 if (!xf86IsPrimaryPci(pCir->PciInfo)
602 && !(pInt || (xf86IsOptionSet(pCir->Options,OPTION_MEMCFG1)
603 && xf86IsOptionSet(pCir->Options,OPTION_MEMCFG2))))
610 pCir->HWCursor = FALSE;
612 switch (pCir->Chipset) {
615 pCir->HWCursor = TRUE;
621 if (xf86GetOptValBool(pCir->Options, OPTION_HW_CURSOR, &pCir->HWCursor))
625 pCir->HWCursor ? "HW" : "SW");
626 if (xf86ReturnOptValBool(pCir->Options, OPTION_NOACCEL, FALSE)) {
627 pCir->NoAccel = TRUE;
633 pCir->NoAccel = TRUE;
640 if (pCir->pEnt->device->chipRev >= 0) {
641 pCir->ChipRev = pCir->pEnt->device->chipRev;
643 pCir->ChipRev);
645 pCir->ChipRev = PCI_DEV_REVISION(pCir->PciInfo);
649 if (pCir->pEnt->device->MemBase != 0) {
650 if (!xf86CheckPciMemBase(pCir->PciInfo, pCir->pEnt->device->MemBase)) {
653 pCir->pEnt->device->MemBase);
656 pCir->FbAddress = pCir->pEnt->device->MemBase;
659 if (PCI_REGION_BASE(pCir->PciInfo, 0, REGION_MEM) != 0) {
662 pCir->FbAddress = PCI_REGION_BASE(pCir->PciInfo, 0, REGION_MEM) & 0xff000000;
672 (unsigned long)pCir->FbAddress);
674 if (pCir->pEnt->device->IOBase != 0) {
676 if (!xf86CheckPciMemBase(pCir->PciInfo, pCir->pEnt->device->IOBase)) {
679 pCir->pEnt->device->IOBase);
682 pCir->IOAddress = pCir->pEnt->device->IOBase;
685 if (PCI_REGION_BASE(pCir->PciInfo, 1, REGION_MEM) != 0) {
686 pCir->IOAddress = PCI_REGION_BASE(pCir->PciInfo, 1, REGION_MEM) & 0xfffff000;
687 pCir->IoMapSize = PCI_REGION_SIZE(pCir->PciInfo, 1);
700 if (xf86ReturnOptValBool(pCir->Options, OPTION_MMIO, FALSE)) {
701 pCir->UseMMIO = TRUE;
705 if (!xf86ReturnOptValBool(pCir->Options, OPTION_MMIO, TRUE)) {
706 pCir->UseMMIO = FALSE;
708 } else if (pCir->IOAddress) {
712 pCir->UseMMIO = TRUE;
715 pCir->UseMMIO = FALSE;
719 pCir->UseMMIO = FALSE;
723 if (pCir->UseMMIO) {
726 (unsigned long)pCir->IOAddress);
734 if (!pCir->UseMMIO) {
736 xf86SetOperatingState(resVgaMem, pCir->pEnt->index, ResUnusedOpr);
738 xf86SetOperatingState(resVga, pCir->pEnt->index, ResUnusedOpr);
742 if (xf86RegisterResources(pCir->pEnt->index, NULL, ResExclusive)) {
765 xf86DoEDID_DDC2(XF86_SCRN_ARG(pScrn),pCir->I2CPtr1)));
772 ((pCir->PciInfo->subvendor_id & 0xffff) == PCI_CHIP_QEMU)) {
773 pCir->NoAccel = TRUE;
795 if (xf86GetOptValBool(pCir->Options,
796 OPTION_SHADOW_FB,&pCir->shadowFB))
798 pCir->shadowFB ? "enabled" : "disabled");
800 if ((s = xf86GetOptValString(pCir->Options, OPTION_ROTATE))) {
803 pCir->shadowFB = TRUE;
804 pCir->rotate = 1;
808 pCir->shadowFB = TRUE;
809 pCir->rotate = -1;
819 if (pCir->shadowFB && (pScrn->depth < 8)) {
822 pCir->shadowFB = FALSE;
823 pCir->rotate = 0;
826 if (pCir->shadowFB && !pCir->NoAccel) {
829 pCir->NoAccel = TRUE;
832 if (pCir->rotate && pCir->HWCursor) {
835 pCir->HWCursor = FALSE;
842 pCir->chip.alp->sr0f = (CARD32)-1;
843 pCir->chip.alp->sr17 = (CARD32)-1;
845 (void) xf86GetOptValULong(pCir->Options, OPTION_MEMCFG1, (unsigned long *)&pCir->chip.alp->sr0f);
846 (void) xf86GetOptValULong(pCir->Options, OPTION_MEMCFG2, (unsigned long *)&pCir->chip.alp->sr17);
851 if (pCir->pEnt->device->videoRam != 0) {
852 pScrn->videoRam = pCir->pEnt->device->videoRam;
853 pCir->IoMapSize = 0x4000; /* 16K for moment */
861 pCir->FbMapSize = pScrn->videoRam * 1024;
864 pCir->properties = 0;
866 if ((pCir->chip.alp->sr0f & 0x18) > 0x8)
867 pCir->properties |= HWCUR64;
869 switch (pCir->Chipset) {
871 pCir->properties |= HWCUR64;
872 pCir->properties |= ACCEL_AUTOSTART;
876 pCir->properties |= ACCEL_AUTOSTART;
888 pCir->MinClock = 12000; /* XXX Guess, need to check this */
890 pCir->MinClock / 1000);
895 if (pCir->pEnt->device->dacSpeeds[0]) {
901 switch (pCir->Chipset) {
950 pCir->MaxClock = speed;
954 pCir->MaxClock / 1000);
962 clockRanges->minClock = pCir->MinClock;
963 clockRanges->maxClock = pCir->MaxClock;
973 switch (pCir->Chipset)
976 pCir->Rounding = 1;
980 pCir->Rounding = 128 >> pCir->BppShift;
984 if (pCir->Chipset != PCI_CHIP_GD5446 &&
985 pCir->Chipset != PCI_CHIP_GD5480) {
987 pCir->NoAccel = TRUE;
999 if (pCir->NoAccel) {
1007 pCir->Rounding * pScrn->bitsPerPixel, 128, 2048,
1010 pCir->FbMapSize,
1019 pCir->Rounding * pScrn->bitsPerPixel, 128, 2048,
1022 pCir->FbMapSize,
1088 if (!pCir->NoAccel) {
1097 pCir->NoAccel = TRUE;
1098 pCir->shadowFB = TRUE;
1104 if (pCir->HWCursor) {
1111 if (pCir->shadowFB) {
1127 CirPtr pCir = CIRPTR(pScrn);
1135 pCir->chip.alp->ModeReg.ExtVga[CR1A] = pCir->chip.alp->SavedReg.ExtVga[CR1A] = hwp->readCrtc(hwp, 0x1A);
1136 pCir->chip.alp->ModeReg.ExtVga[CR1B] = pCir->chip.alp->SavedReg.ExtVga[CR1B] = hwp->readCrtc(hwp, 0x1B);
1137 pCir->chip.alp->ModeReg.ExtVga[CR1D] = pCir->chip.alp->SavedReg.ExtVga[CR1D] = hwp->readCrtc(hwp, 0x1D);
1138 pCir->chip.alp->ModeReg.ExtVga[SR07] = pCir->chip.alp->SavedReg.ExtVga[SR07] = hwp->readSeq(hwp, 0x07);
1139 pCir->chip.alp->ModeReg.ExtVga[SR0E] = pCir->chip.alp->SavedReg.ExtVga[SR0E] = hwp->readSeq(hwp, 0x0E);
1140 pCir->chip.alp->ModeReg.ExtVga[SR12] = pCir->chip.alp->SavedReg.ExtVga[SR12] = hwp->readSeq(hwp, 0x12);
1141 pCir->chip.alp->ModeReg.ExtVga[SR13] = pCir->chip.alp->SavedReg.ExtVga[SR13] = hwp->readSeq(hwp, 0x13);
1142 pCir->chip.alp->ModeReg.ExtVga[SR17] = pCir->chip.alp->SavedReg.ExtVga[SR17] = hwp->readSeq(hwp, 0x17);
1143 pCir->chip.alp->ModeReg.ExtVga[SR1E] = pCir->chip.alp->SavedReg.ExtVga[SR1E] = hwp->readSeq(hwp, 0x1E);
1144 pCir->chip.alp->ModeReg.ExtVga[SR21] = pCir->chip.alp->SavedReg.ExtVga[SR21] = hwp->readSeq(hwp, 0x21);
1145 pCir->chip.alp->ModeReg.ExtVga[SR2D] = pCir->chip.alp->SavedReg.ExtVga[SR2D] = hwp->readSeq(hwp, 0x2D);
1146 pCir->chip.alp->ModeReg.ExtVga[GR17] = pCir->chip.alp->SavedReg.ExtVga[GR17] = hwp->readGr(hwp, 0x17);
1147 pCir->chip.alp->ModeReg.ExtVga[GR18] = pCir->chip.alp->SavedReg.ExtVga[GR18] = hwp->readGr(hwp, 0x18);
1155 pCir->chip.alp->ModeReg.ExtVga[HDR] = pCir->chip.alp->SavedReg.ExtVga[HDR] = hwp->readDacMask(hwp);
1212 CirPtr pCir;
1233 pCir = CIRPTR(pScrn);
1237 pCir->pitch = pScrn->displayWidth * pScrn->bitsPerPixel >> 3;
1243 if ((pCir->Chipset == PCI_CHIP_GD5480 && mode->Clock > 135100) ||
1244 (pCir->Chipset == PCI_CHIP_GD5446 && mode->Clock > 85500)) {
1279 pCir->chip.alp->ModeReg.ExtVga[SR12] = 0;
1280 if ((pCir->properties & HWCUR64) == HWCUR64)
1282 pCir->chip.alp->ModeReg.ExtVga[SR12] = 0x4;
1283 switch (pCir->Chipset)
1286 pCir->chip.alp->ModeReg.ExtVga[SR21] |= 0x10;
1292 pCir->chip.alp->ModeReg.ExtVga[SR12] = 0;
1303 pCir->chip.alp->ModeReg.ExtVga[GR17] |= 0x08;
1304 pCir->chip.alp->ModeReg.ExtVga[GR17] &= ~0x04;
1306 pCir->chip.alp->ModeReg.ExtVga[HDR] = 0;
1308 pCir->chip.alp->ModeReg.ExtVga[SR07] &= 0xe0;
1324 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x10;
1327 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x11;
1330 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x17;
1333 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x17;
1334 pCir->chip.alp->ModeReg.ExtVga[HDR ] = 0xC0;
1337 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x19;
1338 pCir->chip.alp->ModeReg.ExtVga[HDR ] = 0xC0;
1341 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x17;
1342 pCir->chip.alp->ModeReg.ExtVga[HDR ] = 0xC1;
1345 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x19;
1346 pCir->chip.alp->ModeReg.ExtVga[HDR ] = 0xC1;
1349 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x15;
1350 pCir->chip.alp->ModeReg.ExtVga[HDR ] = 0xC5;
1353 pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x19;
1354 pCir->chip.alp->ModeReg.ExtVga[HDR ] = 0xC5;
1364 pCir->chip.alp->ModeReg.ExtVga[GR18] |= 0x20;
1366 pCir->chip.alp->ModeReg.ExtVga[GR18] &= ~0x20;
1370 switch (pCir->Chipset)
1376 if (pCir->UseMMIO)
1378 pCir->chip.alp->ModeReg.ExtVga[SR17] =
1379 (pCir->chip.alp->ModeReg.ExtVga[SR17] & ~0x40) | 4;
1380 ErrorF("UseMMIO: SR17=%2X\n", (int) (pCir->chip.alp->ModeReg.ExtVga[SR17]));
1383 ErrorF("SR2D=%2X\n", (int) (pCir->chip.alp->ModeReg.ExtVga[SR17]));
1385 pCir->chip.alp->ModeReg.ExtVga[SR2D] |= 0xC0;
1390 pCir->chip.alp->ModeReg.ExtVga[CR1A] = 0x00;
1397 pCir->chip.alp->ModeReg.ExtVga[CR1B] &= 0xAF;
1398 pCir->chip.alp->ModeReg.ExtVga[CR1B] |= (width >> (3+4)) & 0x10;
1399 pCir->chip.alp->ModeReg.ExtVga[CR1B] |= (width >> (3+3)) & 0x40;
1400 pCir->chip.alp->ModeReg.ExtVga[CR1B] |= 0x22;
1405 alpRestore(hwp,&pCir->chip.alp->ModeReg);
1406 AlpSetClock(pCir, hwp, mode->SynthClock);
1432 CirPtr pCir;
1440 pCir = CIRPTR(pScrn);
1442 alpReg = &pCir->chip.alp->SavedReg;
1461 CirPtr pCir;
1474 pCir = CIRPTR(pScrn);
1481 if (!CirMapMem(pCir, pScrn->scrnIndex))
1486 switch (pCir->Chipset)
1491 if(pCir->UseMMIO)
1492 vgaHWSetMmioFuncs(hwp, pCir->IOBase, -0x3C0);
1535 if (pCir->rotate) {
1543 if(pCir->shadowFB) {
1544 pCir->ShadowPitch = BitmapBytePad(pScrn->bitsPerPixel * width);
1545 pCir->ShadowPtr = malloc(pCir->ShadowPitch * height);
1546 displayWidth = pCir->ShadowPitch / (pScrn->bitsPerPixel >> 3);
1547 FbBase = pCir->ShadowPtr;
1549 pCir->ShadowPtr = NULL;
1550 FbBase = pCir->FbBase;
1629 pCir->offscreen_offset = pScrn->videoRam*1024;
1630 pCir->offscreen_size = pScrn->videoRam * 1024 - pScrn->virtualY *
1635 pCir->offscreen_offset, pCir->offscreen_size);
1639 if (pCir->HWCursor) { /* Initialize HW cursor layer */
1641 if ((pCir->properties & HWCUR64)
1642 && (pCir->offscreen_size >= 64*8*2)) {
1644 pCir->offscreen_size -= 64*8*2;
1645 pCir->offscreen_offset -= 64*8*2;
1646 } else if (pCir->offscreen_size >= 32*4*2) {
1648 pCir->offscreen_size -= 32*8*2;
1649 pCir->offscreen_offset -= 32*8*2;
1653 if (!pCir->NoAccel) { /* Initialize XAA functions */
1656 if (!(pCir->UseMMIO ? AlpXAAInitMMIO(pScreen) :
1664 pCir->DGAModeInit = AlpModeInit;
1674 if (pCir->HWCursor) {
1683 if (pCir->shadowFB) {
1686 if(pCir->rotate) {
1687 if (!pCir->PointerMoved) {
1688 pCir->PointerMoved = pScrn->PointerMoved;
1712 pScrn->memPhysBase = pCir->FbAddress;
1728 pCir->CloseScreen = pScreen->CloseScreen;
1801 CirPtr pCir = CIRPTR(pScrn);
1812 if (!pCir->NoAccel)
1813 pCir->InitAccel(pScrn);
1859 CirPtr pCir = CIRPTR(pScrn);
1864 CirUnmapMem(pCir, pScrn->scrnIndex);
1868 if (pCir->AccelInfoRec)
1869 XAADestroyInfoRec(pCir->AccelInfoRec);
1870 pCir->AccelInfoRec = NULL;
1872 if (pCir->CursorInfoRec)
1873 xf86DestroyCursorInfoRec(pCir->CursorInfoRec);
1874 pCir->CursorInfoRec = NULL;
1875 if (pCir->DGAModes)
1876 free(pCir->DGAModes);
1877 pCir->DGAnumModes = 0;
1878 pCir->DGAModes = NULL;
1887 pScreen->CloseScreen = pCir->CloseScreen;
1951 AlpSetClock(CirPtr pCir, vgaHWPtr hwp, int freq)
1961 if (!CirrusFindClock(&ffreq, pCir->MaxClock, &num, &den))
2057 CirPtr pCir = CIRPTR(pScrn);
2058 AlpPtr pAlp = ALPPTR(pCir);
2075 switch (pCir->Chipset) {
2126 CirPtr pCir = CIRPTR(pScrn);
2127 AlpPtr pAlp = ALPPTR(pCir);
2129 if (pCir->offscreen_size >= 8 && pCir->Chipset == PCI_CHIP_GD7548) {
2130 pCir->offscreen_offset -= 8;
2131 pCir->offscreen_size -= 8;
2132 pAlp->monoPattern8x8 = pCir->offscreen_offset;
2144 box.y2= pCir->offscreen_offset / pCir->pitch;