Cross Reference: /xsrc/external/mit/xf86-video-cirrus/dist/src/alp

Lines Matching refs:ModeReg
1135 	pCir->chip.alp->ModeReg.ExtVga[CR1A] = pCir->chip.alp->SavedReg.ExtVga[CR1A] = hwp->readCrtc(hwp, 0x1A);
1136 	pCir->chip.alp->ModeReg.ExtVga[CR1B] = pCir->chip.alp->SavedReg.ExtVga[CR1B] = hwp->readCrtc(hwp, 0x1B);
1137 	pCir->chip.alp->ModeReg.ExtVga[CR1D] = pCir->chip.alp->SavedReg.ExtVga[CR1D] = hwp->readCrtc(hwp, 0x1D);
1138 	pCir->chip.alp->ModeReg.ExtVga[SR07] = pCir->chip.alp->SavedReg.ExtVga[SR07] = hwp->readSeq(hwp, 0x07);
1139 	pCir->chip.alp->ModeReg.ExtVga[SR0E] = pCir->chip.alp->SavedReg.ExtVga[SR0E] = hwp->readSeq(hwp, 0x0E);
1140 	pCir->chip.alp->ModeReg.ExtVga[SR12] = pCir->chip.alp->SavedReg.ExtVga[SR12] = hwp->readSeq(hwp, 0x12);
1141 	pCir->chip.alp->ModeReg.ExtVga[SR13] = pCir->chip.alp->SavedReg.ExtVga[SR13] = hwp->readSeq(hwp, 0x13);
1142 	pCir->chip.alp->ModeReg.ExtVga[SR17] = pCir->chip.alp->SavedReg.ExtVga[SR17] = hwp->readSeq(hwp, 0x17);
1143 	pCir->chip.alp->ModeReg.ExtVga[SR1E] = pCir->chip.alp->SavedReg.ExtVga[SR1E] = hwp->readSeq(hwp, 0x1E);
1144 	pCir->chip.alp->ModeReg.ExtVga[SR21] = pCir->chip.alp->SavedReg.ExtVga[SR21] = hwp->readSeq(hwp, 0x21);
1145 	pCir->chip.alp->ModeReg.ExtVga[SR2D] = pCir->chip.alp->SavedReg.ExtVga[SR2D] = hwp->readSeq(hwp, 0x2D);
1146 	pCir->chip.alp->ModeReg.ExtVga[GR17] = pCir->chip.alp->SavedReg.ExtVga[GR17] = hwp->readGr(hwp, 0x17);
1147 	pCir->chip.alp->ModeReg.ExtVga[GR18] = pCir->chip.alp->SavedReg.ExtVga[GR18] = hwp->readGr(hwp, 0x18);
1155 	pCir->chip.alp->ModeReg.ExtVga[HDR] = pCir->chip.alp->SavedReg.ExtVga[HDR] = hwp->readDacMask(hwp);
1273 	/* Initialise the ModeReg values */
1279 	pCir->chip.alp->ModeReg.ExtVga[SR12] = 0;
1282             pCir->chip.alp->ModeReg.ExtVga[SR12] = 0x4;
1286 	      pCir->chip.alp->ModeReg.ExtVga[SR21] |= 0x10;
1292 	    pCir->chip.alp->ModeReg.ExtVga[SR12] = 0;
1296 		hwp->ModeReg.CRTC[0x17] |= 0x04;
1303 	pCir->chip.alp->ModeReg.ExtVga[GR17] |= 0x08;
1304 	pCir->chip.alp->ModeReg.ExtVga[GR17] &= ~0x04;
1306 	pCir->chip.alp->ModeReg.ExtVga[HDR] = 0;
1308 	pCir->chip.alp->ModeReg.ExtVga[SR07] &= 0xe0;
1315 		hwp->ModeReg.MiscOutReg &= ~0x01;
1318 		hwp->ModeReg.MiscOutReg |= 0x01;
1324 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x10;
1327 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x11;
1330 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x17;
1333 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x17;
1334 		pCir->chip.alp->ModeReg.ExtVga[HDR ]  = 0xC0;
1337 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x19;
1338 		pCir->chip.alp->ModeReg.ExtVga[HDR ]  = 0xC0;
1341 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x17;
1342 		pCir->chip.alp->ModeReg.ExtVga[HDR ]  = 0xC1;
1345 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x19;
1346 		pCir->chip.alp->ModeReg.ExtVga[HDR ]  = 0xC1;
1349 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x15;
1350 		pCir->chip.alp->ModeReg.ExtVga[HDR ]  = 0xC5;
1353 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x19;
1354 		pCir->chip.alp->ModeReg.ExtVga[HDR ]  = 0xC5;
1364 		pCir->chip.alp->ModeReg.ExtVga[GR18] |= 0x20;
1366 		pCir->chip.alp->ModeReg.ExtVga[GR18] &= ~0x20;
1378 	      pCir->chip.alp->ModeReg.ExtVga[SR17] =
1379 		(pCir->chip.alp->ModeReg.ExtVga[SR17] & ~0x40) | 4;
1380 	      ErrorF("UseMMIO: SR17=%2X\n", (int) (pCir->chip.alp->ModeReg.ExtVga[SR17]));
1383 	    ErrorF("SR2D=%2X\n", (int) (pCir->chip.alp->ModeReg.ExtVga[SR17]));
1385 	    pCir->chip.alp->ModeReg.ExtVga[SR2D] |= 0xC0;
1390 	pCir->chip.alp->ModeReg.ExtVga[CR1A] = 0x00;
1395 	hwp->ModeReg.CRTC[0x13] = width >> 3;
1397 	pCir->chip.alp->ModeReg.ExtVga[CR1B] &= 0xAF;
1398 	pCir->chip.alp->ModeReg.ExtVga[CR1B] |= (width >> (3+4)) & 0x10;
1399 	pCir->chip.alp->ModeReg.ExtVga[CR1B] |= (width >> (3+3)) & 0x40;
1400 	pCir->chip.alp->ModeReg.ExtVga[CR1B] |= 0x22;
1404 	hwp->writeMiscOut(hwp, hwp->ModeReg.MiscOutReg); 
1405 	alpRestore(hwp,&pCir->chip.alp->ModeReg);
1408 	vgaHWRestore(pScrn, &hwp->ModeReg, VGA_SR_MODE | VGA_SR_CMAP);