Cross Reference: /xsrc/external/mit/xf86-video-cirrus/dist/src/alp

Lines Matching refs:alp
68 #include "alp.h"
225 	((CirPtr)pScrn->driverPrivate)->chip.alp = xnfcalloc(sizeof(AlpRec),1);
276     if (pCir->chip.alp->sr0f != (CARD32)-1) {
278 	hwp->writeSeq(hwp, 0x0F, pCir->chip.alp->sr0f);
281 	pCir->chip.alp->sr0f = hwp->readSeq(hwp, 0x0F);
284 	       (unsigned int)pCir->chip.alp->sr0f);
289 	switch (pCir->chip.alp->sr0f & 0x18) {
305 	switch (pCir->chip.alp->sr0f & 0x18) {
311 	    if (pCir->chip.alp->sr0f & 0x80)
319 	if (pCir->chip.alp->sr17 != (CARD32)-1) {
321 	    hwp->writeSeq(hwp, 0x17, pCir->chip.alp->sr17);
324 	    pCir->chip.alp->sr17 = hwp->readSeq(hwp, 0x17);
327 		   (unsigned int)pCir->chip.alp->sr17);
329 	if ((pCir->chip.alp->sr0f & 0x18) == 0x18) {
330 	    if (pCir->chip.alp->sr0f & 0x80) {
331 		if (pCir->chip.alp->sr17 & 0x80)
333 		else if (pCir->chip.alp->sr17 & 0x02)
338 		if ((pCir->chip.alp->sr17 & 80) == 0)
345 	if (pCir->chip.alp->sr17 != (CARD32)-1) {
347 	    hwp->writeSeq(hwp, 0x17, pCir->chip.alp->sr17);
350 	    pCir->chip.alp->sr17 = hwp->readSeq(hwp, 0x17);
353 		   (unsigned int)pCir->chip.alp->sr17);
355 	if ((pCir->chip.alp->sr0f & 0x18) == 0x18) {	/* 2 or 4 MB */
357 	    if (pCir->chip.alp->sr0f & 0x80)	/* Second bank enable */
360 	if (pCir->chip.alp->sr17 & 0x80)
366 	switch (pCir->chip.alp->sr0f & 0x90) {
842 	pCir->chip.alp->sr0f = (CARD32)-1;
843 	pCir->chip.alp->sr17 = (CARD32)-1;
845 	(void) xf86GetOptValULong(pCir->Options, OPTION_MEMCFG1, (unsigned long *)&pCir->chip.alp->sr0f);
846 	(void) xf86GetOptValULong(pCir->Options, OPTION_MEMCFG2, (unsigned long *)&pCir->chip.alp->sr17);
866 	if ((pCir->chip.alp->sr0f & 0x18) > 0x8)
1135 	pCir->chip.alp->ModeReg.ExtVga[CR1A] = pCir->chip.alp->SavedReg.ExtVga[CR1A] = hwp->readCrtc(hwp, 0x1A);
1136 	pCir->chip.alp->ModeReg.ExtVga[CR1B] = pCir->chip.alp->SavedReg.ExtVga[CR1B] = hwp->readCrtc(hwp, 0x1B);
1137 	pCir->chip.alp->ModeReg.ExtVga[CR1D] = pCir->chip.alp->SavedReg.ExtVga[CR1D] = hwp->readCrtc(hwp, 0x1D);
1138 	pCir->chip.alp->ModeReg.ExtVga[SR07] = pCir->chip.alp->SavedReg.ExtVga[SR07] = hwp->readSeq(hwp, 0x07);
1139 	pCir->chip.alp->ModeReg.ExtVga[SR0E] = pCir->chip.alp->SavedReg.ExtVga[SR0E] = hwp->readSeq(hwp, 0x0E);
1140 	pCir->chip.alp->ModeReg.ExtVga[SR12] = pCir->chip.alp->SavedReg.ExtVga[SR12] = hwp->readSeq(hwp, 0x12);
1141 	pCir->chip.alp->ModeReg.ExtVga[SR13] = pCir->chip.alp->SavedReg.ExtVga[SR13] = hwp->readSeq(hwp, 0x13);
1142 	pCir->chip.alp->ModeReg.ExtVga[SR17] = pCir->chip.alp->SavedReg.ExtVga[SR17] = hwp->readSeq(hwp, 0x17);
1143 	pCir->chip.alp->ModeReg.ExtVga[SR1E] = pCir->chip.alp->SavedReg.ExtVga[SR1E] = hwp->readSeq(hwp, 0x1E);
1144 	pCir->chip.alp->ModeReg.ExtVga[SR21] = pCir->chip.alp->SavedReg.ExtVga[SR21] = hwp->readSeq(hwp, 0x21);
1145 	pCir->chip.alp->ModeReg.ExtVga[SR2D] = pCir->chip.alp->SavedReg.ExtVga[SR2D] = hwp->readSeq(hwp, 0x2D);
1146 	pCir->chip.alp->ModeReg.ExtVga[GR17] = pCir->chip.alp->SavedReg.ExtVga[GR17] = hwp->readGr(hwp, 0x17);
1147 	pCir->chip.alp->ModeReg.ExtVga[GR18] = pCir->chip.alp->SavedReg.ExtVga[GR18] = hwp->readGr(hwp, 0x18);
1155 	pCir->chip.alp->ModeReg.ExtVga[HDR] = pCir->chip.alp->SavedReg.ExtVga[HDR] = hwp->readDacMask(hwp);
1279 	pCir->chip.alp->ModeReg.ExtVga[SR12] = 0;
1282             pCir->chip.alp->ModeReg.ExtVga[SR12] = 0x4;
1286 	      pCir->chip.alp->ModeReg.ExtVga[SR21] |= 0x10;
1292 	    pCir->chip.alp->ModeReg.ExtVga[SR12] = 0;
1303 	pCir->chip.alp->ModeReg.ExtVga[GR17] |= 0x08;
1304 	pCir->chip.alp->ModeReg.ExtVga[GR17] &= ~0x04;
1306 	pCir->chip.alp->ModeReg.ExtVga[HDR] = 0;
1308 	pCir->chip.alp->ModeReg.ExtVga[SR07] &= 0xe0;
1324 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x10;
1327 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x11;
1330 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x17;
1333 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x17;
1334 		pCir->chip.alp->ModeReg.ExtVga[HDR ]  = 0xC0;
1337 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x19;
1338 		pCir->chip.alp->ModeReg.ExtVga[HDR ]  = 0xC0;
1341 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x17;
1342 		pCir->chip.alp->ModeReg.ExtVga[HDR ]  = 0xC1;
1345 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x19;
1346 		pCir->chip.alp->ModeReg.ExtVga[HDR ]  = 0xC1;
1349 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x15;
1350 		pCir->chip.alp->ModeReg.ExtVga[HDR ]  = 0xC5;
1353 		pCir->chip.alp->ModeReg.ExtVga[SR07] |= 0x19;
1354 		pCir->chip.alp->ModeReg.ExtVga[HDR ]  = 0xC5;
1364 		pCir->chip.alp->ModeReg.ExtVga[GR18] |= 0x20;
1366 		pCir->chip.alp->ModeReg.ExtVga[GR18] &= ~0x20;
1378 	      pCir->chip.alp->ModeReg.ExtVga[SR17] =
1379 		(pCir->chip.alp->ModeReg.ExtVga[SR17] & ~0x40) | 4;
1380 	      ErrorF("UseMMIO: SR17=%2X\n", (int) (pCir->chip.alp->ModeReg.ExtVga[SR17]));
1383 	    ErrorF("SR2D=%2X\n", (int) (pCir->chip.alp->ModeReg.ExtVga[SR17]));
1385 	    pCir->chip.alp->ModeReg.ExtVga[SR2D] |= 0xC0;
1390 	pCir->chip.alp->ModeReg.ExtVga[CR1A] = 0x00;
1397 	pCir->chip.alp->ModeReg.ExtVga[CR1B] &= 0xAF;
1398 	pCir->chip.alp->ModeReg.ExtVga[CR1B] |= (width >> (3+4)) & 0x10;
1399 	pCir->chip.alp->ModeReg.ExtVga[CR1B] |= (width >> (3+3)) & 0x40;
1400 	pCir->chip.alp->ModeReg.ExtVga[CR1B] |= 0x22;
1405 	alpRestore(hwp,&pCir->chip.alp->ModeReg);
1442 	alpReg = &pCir->chip.alp->SavedReg;