Cross Reference: /xsrc/external/mit/xf86-video-cirrus/dist/src/lg

Lines Matching refs:ModeReg
1043     pCir->chip.lg->ModeReg.ExtVga[CR1A] =
1045     pCir->chip.lg->ModeReg.ExtVga[CR1B] =
1047     pCir->chip.lg->ModeReg.ExtVga[CR1D] =
1049     pCir->chip.lg->ModeReg.ExtVga[CR1E] =
1051     pCir->chip.lg->ModeReg.ExtVga[SR07] =
1053     pCir->chip.lg->ModeReg.ExtVga[SR0E] =
1055     pCir->chip.lg->ModeReg.ExtVga[SR1E] =
1058     pCir->chip.lg->ModeReg.FORMAT =
1061     pCir->chip.lg->ModeReg.VSC =
1064     pCir->chip.lg->ModeReg.DTTC =
1068         pCir->chip.lg->ModeReg.TileCtrl =
1072     pCir->chip.lg->ModeReg.TILE =
1076         pCir->chip.lg->ModeReg.BCLK =
1079         pCir->chip.lg->ModeReg.BCLK =
1082     pCir->chip.lg->ModeReg.CONTROL =
1085     pCir->chip.lg->ModeReg.RIFCtrl =
1088     pCir->chip.lg->ModeReg.RACCtrl =
1138      * Initialise the ModeReg values.
1145         hwp->ModeReg.CRTC[0x17] |= 0x04;
1151     hwp->ModeReg.MiscOutReg |= 0x01;
1157     hwp->ModeReg.MiscOutReg &= ~0x01;
1163     pCir->chip.lg->ModeReg.ExtVga[CR1A] =
1170     hwp->ModeReg.CRTC[0x13] = (width + 7) >> 3;
1174     pCir->chip.lg->ModeReg.ExtVga[CR1B] &= 0xEF;
1175     pCir->chip.lg->ModeReg.ExtVga[CR1B] |=
1177     pCir->chip.lg->ModeReg.ExtVga[CR1B] |= 0x22;
1178     pCir->chip.lg->ModeReg.ExtVga[CR1D] =
1184     pCir->chip.lg->ModeReg.VSC = 0x10000000;
1189     pCir->chip.lg->ModeReg.ExtVga[CR1E] = 0x00;
1190     pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1192     pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1194     pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1196     pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1198     pCir->chip.lg->ModeReg.ExtVga[CR1E] |=
1200     pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1202     pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1204     pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1209     pCir->chip.lg->ModeReg.TILE = lineData->tilesPerLine & 0x3F;
1212         pCir->chip.lg->ModeReg.FORMAT = 0x0000;
1214         pCir->chip.lg->ModeReg.DTTC =
1215                 (pCir->chip.lg->ModeReg.TILE << 8) |
1218         pCir->chip.lg->ModeReg.CONTROL = 0x0000 |
1232             pCir->chip.lg->ModeReg.DTTC =
1233                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1240             pCir->chip.lg->ModeReg.DTTC =
1241                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1248             pCir->chip.lg->ModeReg.DTTC =
1249                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1256             pCir->chip.lg->ModeReg.DTTC =
1257                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1264             pCir->chip.lg->ModeReg.DTTC =
1265                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1272         pCir->chip.lg->ModeReg.FORMAT = 0x1400;
1275             pCir->chip.lg->ModeReg.FORMAT = 0x1600;
1277         pCir->chip.lg->ModeReg.DTTC =
1278                                 (pCir->chip.lg->ModeReg.TILE << 8) |
1281         pCir->chip.lg->ModeReg.CONTROL = 0x2000 |
1289             pCir->chip.lg->ModeReg.DTTC =
1290                     (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1297             pCir->chip.lg->ModeReg.DTTC =
1298                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1305             pCir->chip.lg->ModeReg.DTTC =
1306                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1314             pCir->chip.lg->ModeReg.DTTC =
1315                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1318             pCir->chip.lg->ModeReg.DTTC =
1319                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1323         pCir->chip.lg->ModeReg.FORMAT = 0x2400;
1325         pCir->chip.lg->ModeReg.DTTC =
1326                                 (pCir->chip.lg->ModeReg.TILE << 8) |
1329         pCir->chip.lg->ModeReg.CONTROL = 0x4000 |
1337             pCir->chip.lg->ModeReg.DTTC =
1338                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1345             pCir->chip.lg->ModeReg.DTTC =
1346                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1354             pCir->chip.lg->ModeReg.DTTC =
1355                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1362             pCir->chip.lg->ModeReg.DTTC =
1363                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1370             pCir->chip.lg->ModeReg.DTTC =
1371                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1375         pCir->chip.lg->ModeReg.FORMAT = 0x3400;
1377         pCir->chip.lg->ModeReg.DTTC =
1378                                 (pCir->chip.lg->ModeReg.TILE << 8) |
1381         pCir->chip.lg->ModeReg.CONTROL = 0x6000 |
1389             pCir->chip.lg->ModeReg.DTTC =
1390                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1397             pCir->chip.lg->ModeReg.DTTC =
1398                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1406             pCir->chip.lg->ModeReg.DTTC =
1407                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1417             pCir->chip.lg->ModeReg.DTTC =
1418                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1421             pCir->chip.lg->ModeReg.DTTC =
1422                             (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1434     pCir->chip.lg->ModeReg.DTTC |= (pCir->chip.lg->memInterleave << 8);
1435     pCir->chip.lg->ModeReg.TILE |= pCir->chip.lg->memInterleave & 0xC0;
1442         pCir->chip.lg->ModeReg.TileCtrl =
1443                                 pCir->chip.lg->ModeReg.DTTC & 0xFFC0;
1449         if (pCir->chip.lg->ModeReg.DTTC & 0x0040) {
1454             pCir->chip.lg->ModeReg.DTTC =
1455                         (pCir->chip.lg->ModeReg.DTTC & 0xC0FF) |
1456                         ((pCir->chip.lg->ModeReg.DTTC & 0x3F00) << 1);
1464     hwp->writeMiscOut(hwp, hwp->ModeReg.MiscOutReg);
1467     pCir->chip.lg->ModeReg.ExtVga[SR0E] = (clockData >> 8) & 0xFF;
1468     pCir->chip.lg->ModeReg.ExtVga[SR1E] = clockData & 0xFF;
1473     LgRestoreLgRegs(pScrn, &pCir->chip.lg->ModeReg);
1478     vgaHWRestore(pScrn, &hwp->ModeReg, VGA_SR_MODE | VGA_SR_CMAP);