Lines Matching refs:SavedReg
1041 vgaHWSave(pScrn, &VGAHWPTR(pScrn)->SavedReg, VGA_SR_ALL);
1044 pCir->chip.lg->SavedReg.ExtVga[CR1A] = hwp->readCrtc(hwp, 0x1A);
1046 pCir->chip.lg->SavedReg.ExtVga[CR1B] = hwp->readCrtc(hwp, 0x1B);
1048 pCir->chip.lg->SavedReg.ExtVga[CR1D] = hwp->readCrtc(hwp, 0x1D);
1050 pCir->chip.lg->SavedReg.ExtVga[CR1E] = hwp->readCrtc(hwp, 0x1E);
1052 pCir->chip.lg->SavedReg.ExtVga[SR07] = hwp->readSeq(hwp, 0x07);
1054 pCir->chip.lg->SavedReg.ExtVga[SR0E] = hwp->readSeq(hwp, 0x0E);
1056 pCir->chip.lg->SavedReg.ExtVga[SR1E] = hwp->readSeq(hwp, 0x1E);
1059 pCir->chip.lg->SavedReg.FORMAT = memrw(0xC0);
1062 pCir->chip.lg->SavedReg.VSC = memrl(0x3FC);
1065 pCir->chip.lg->SavedReg.DTTC = memrw(0xEA);
1069 pCir->chip.lg->SavedReg.TileCtrl = memrw(0x2C4);
1073 pCir->chip.lg->SavedReg.TILE = memrb(0x407);
1077 pCir->chip.lg->SavedReg.BCLK = memrb(0x2C0);
1080 pCir->chip.lg->SavedReg.BCLK = memrb(0x8C);
1083 pCir->chip.lg->SavedReg.CONTROL = memrw(0x402);
1086 pCir->chip.lg->SavedReg.RIFCtrl = memrw(0x200);
1089 pCir->chip.lg->SavedReg.RACCtrl = memrw(0x202);
1580 vgaReg = &hwp->SavedReg;
1581 lgReg = &pCir->chip.lg->SavedReg;