Lines Matching refs:pCir
119 static CARD16 LgSetClock(CirPtr pCir, vgaHWPtr hwp, int freq);
276 CirPtr pCir;
288 pCir = CIRPTR(pScrn);
289 pCir->chip.lg->oldBitmask = 0x00000000;
343 CirPtr pCir = CIRPTR(pScrn);
349 if (!CirMapMem(pCir, pScrn->scrnIndex))
361 MonInfo = xf86DoEDID_DDC2(XF86_SCRN_ARG(pScrn), pCir->I2CPtr1);
377 CirUnmapMem(pCir, pScrn->scrnIndex);
388 CirPtr pCir;
434 pCir = CIRPTR(pScrn);
435 pCir->pScrn = pScrn;
438 pCir->PIOReg = hwp->PIOOffset + 0x3CE;
440 pCir->PIOReg = 0x3CE;
446 pCir->pEnt = xf86GetEntityInfo(pScrn->entityList[0]);
447 if (pCir->pEnt->location.type != BUS_PCI)
449 pCir->Chipset = pCir->pEnt->chipset;
454 pCir->PciInfo = xf86GetPciInfoForEntity(pCir->pEnt->index);
456 pCir->PciTag = pciTag(PCI_DEV_BUS(pCir->PciInfo),
457 PCI_DEV_DEV(pCir->PciInfo), PCI_DEV_FUNC(pCir->PciInfo));
463 int10InfoPtr = xf86InitInt10(pCir->pEnt->index);
548 if (!(pCir->Options = malloc(sizeof(LgOptions))))
550 memcpy(pCir->Options, LgOptions, sizeof(LgOptions));
553 pCir->Options);
557 pCir->HWCursor = FALSE;
558 if (xf86GetOptValBool(pCir->Options, OPTION_HW_CURSOR,
559 &pCir->HWCursor))
563 pCir->HWCursor ? "HW" : "SW");
564 if (xf86ReturnOptValBool(pCir->Options, OPTION_NOACCEL, FALSE)) {
565 pCir->NoAccel = TRUE;
577 if (pCir->pEnt->device->chipRev >= 0) {
578 pCir->ChipRev = pCir->pEnt->device->chipRev;
580 "ChipRev override: %d\n", pCir->ChipRev);
582 pCir->ChipRev = PCI_DEV_REVISION(pCir->PciInfo);
589 if (PCI_CHIP_GD5465 == pCir->Chipset) {
600 if (pCir->pEnt->device->MemBase != 0) {
605 if (!xf86CheckPciMemBase(pCir->PciInfo,
606 pCir->pEnt->device->MemBase)) {
610 pCir->pEnt->device->MemBase);
613 pCir->FbAddress = pCir->pEnt->device->MemBase;
616 if (PCI_REGION_BASE(pCir->PciInfo,
619 pCir->FbAddress = PCI_REGION_BASE(pCir->PciInfo,
633 (unsigned long) pCir->FbAddress);
638 if (pCir->pEnt->device->IOBase != 0) {
643 if (!xf86CheckPciMemBase(pCir->PciInfo,
644 pCir->pEnt->device->IOBase)) {
648 pCir->pEnt->device->IOBase);
651 pCir->IOAddress = pCir->pEnt->device->IOBase;
654 if (PCI_REGION_BASE(pCir->PciInfo,
657 pCir->IOAddress = PCI_REGION_BASE(pCir->PciInfo,
670 (unsigned long) pCir->IOAddress);
676 if (pCir->pEnt->device->videoRam != 0) {
677 pScrn->videoRam = pCir->pEnt->device->videoRam;
687 pCir->chip.lg->memInterleave = 0x40;
692 pCir->chip.lg->memInterleave = 0x80;
697 pCir->chip.lg->memInterleave = 0x00;
703 pCir->FbMapSize = pScrn->videoRam * 1024;
707 pCir->IoMapSize = 0x4000;
715 xf86SetOperatingState(resVgaMem, pCir->pEnt->index, ResUnusedOpr);
720 if (xf86RegisterResources(pCir->pEnt->index, NULL, ResExclusive)) {
754 if (xf86GetOptValBool(pCir->Options,
756 &pCir->shadowFB))
759 pCir->shadowFB ? "enabled" : "disabled");
761 if ((s = xf86GetOptValString(pCir->Options, OPTION_ROTATE))) {
766 pCir->shadowFB = TRUE;
767 pCir->rotate = 1;
772 pCir->shadowFB = TRUE;
773 pCir->rotate = -1;
786 if (pCir->shadowFB && !pCir->NoAccel) {
790 pCir->NoAccel = TRUE;
793 if (pCir->rotate && pCir->HWCursor) {
796 pCir->HWCursor = FALSE;
814 pCir->MinClock = 12000;
817 pCir->MinClock / 1000);
822 if (pCir->pEnt->device->dacSpeeds[0]) {
828 switch (pCir->Chipset) {
864 pCir->MaxClock = speed;
868 pCir->MaxClock / 1000);
876 clockRanges->minClock = pCir->MinClock;
877 clockRanges->maxClock = pCir->MaxClock;
908 pCir->Rounding = 128 >> pCir->BppShift;
929 pCir->FbMapSize, LOOKUP_BEST_REFRESH);
931 pCir->chip.lg->lineDataIndex =
994 if (!pCir->NoAccel) {
1003 pCir->NoAccel = TRUE;
1004 pCir->shadowFB = TRUE;
1011 if (pCir->HWCursor) {
1018 if (pCir->shadowFB) {
1034 CirPtr pCir = CIRPTR(pScrn);
1043 pCir->chip.lg->ModeReg.ExtVga[CR1A] =
1044 pCir->chip.lg->SavedReg.ExtVga[CR1A] = hwp->readCrtc(hwp, 0x1A);
1045 pCir->chip.lg->ModeReg.ExtVga[CR1B] =
1046 pCir->chip.lg->SavedReg.ExtVga[CR1B] = hwp->readCrtc(hwp, 0x1B);
1047 pCir->chip.lg->ModeReg.ExtVga[CR1D] =
1048 pCir->chip.lg->SavedReg.ExtVga[CR1D] = hwp->readCrtc(hwp, 0x1D);
1049 pCir->chip.lg->ModeReg.ExtVga[CR1E] =
1050 pCir->chip.lg->SavedReg.ExtVga[CR1E] = hwp->readCrtc(hwp, 0x1E);
1051 pCir->chip.lg->ModeReg.ExtVga[SR07] =
1052 pCir->chip.lg->SavedReg.ExtVga[SR07] = hwp->readSeq(hwp, 0x07);
1053 pCir->chip.lg->ModeReg.ExtVga[SR0E] =
1054 pCir->chip.lg->SavedReg.ExtVga[SR0E] = hwp->readSeq(hwp, 0x0E);
1055 pCir->chip.lg->ModeReg.ExtVga[SR1E] =
1056 pCir->chip.lg->SavedReg.ExtVga[SR1E] = hwp->readSeq(hwp, 0x1E);
1058 pCir->chip.lg->ModeReg.FORMAT =
1059 pCir->chip.lg->SavedReg.FORMAT = memrw(0xC0);
1061 pCir->chip.lg->ModeReg.VSC =
1062 pCir->chip.lg->SavedReg.VSC = memrl(0x3FC);
1064 pCir->chip.lg->ModeReg.DTTC =
1065 pCir->chip.lg->SavedReg.DTTC = memrw(0xEA);
1067 if (pCir->Chipset == PCI_CHIP_GD5465) {
1068 pCir->chip.lg->ModeReg.TileCtrl =
1069 pCir->chip.lg->SavedReg.TileCtrl = memrw(0x2C4);
1072 pCir->chip.lg->ModeReg.TILE =
1073 pCir->chip.lg->SavedReg.TILE = memrb(0x407);
1075 if (pCir->Chipset == PCI_CHIP_GD5465)
1076 pCir->chip.lg->ModeReg.BCLK =
1077 pCir->chip.lg->SavedReg.BCLK = memrb(0x2C0);
1079 pCir->chip.lg->ModeReg.BCLK =
1080 pCir->chip.lg->SavedReg.BCLK = memrb(0x8C);
1082 pCir->chip.lg->ModeReg.CONTROL =
1083 pCir->chip.lg->SavedReg.CONTROL = memrw(0x402);
1085 pCir->chip.lg->ModeReg.RIFCtrl =
1086 pCir->chip.lg->SavedReg.RIFCtrl = memrw(0x200);
1088 pCir->chip.lg->ModeReg.RACCtrl =
1089 pCir->chip.lg->SavedReg.RACCtrl = memrw(0x202);
1101 CirPtr pCir;
1118 pCir = CIRPTR(pScrn);
1163 pCir->chip.lg->ModeReg.ExtVga[CR1A] =
1174 pCir->chip.lg->ModeReg.ExtVga[CR1B] &= 0xEF;
1175 pCir->chip.lg->ModeReg.ExtVga[CR1B] |=
1177 pCir->chip.lg->ModeReg.ExtVga[CR1B] |= 0x22;
1178 pCir->chip.lg->ModeReg.ExtVga[CR1D] =
1184 pCir->chip.lg->ModeReg.VSC = 0x10000000;
1189 pCir->chip.lg->ModeReg.ExtVga[CR1E] = 0x00;
1190 pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1192 pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1194 pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1196 pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1198 pCir->chip.lg->ModeReg.ExtVga[CR1E] |=
1200 pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1202 pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1204 pCir->chip.lg->ModeReg.ExtVga[CR1E] |= (
1207 lineData = &LgLineData[pCir->chip.lg->lineDataIndex];
1209 pCir->chip.lg->ModeReg.TILE = lineData->tilesPerLine & 0x3F;
1212 pCir->chip.lg->ModeReg.FORMAT = 0x0000;
1214 pCir->chip.lg->ModeReg.DTTC =
1215 (pCir->chip.lg->ModeReg.TILE << 8) |
1218 pCir->chip.lg->ModeReg.CONTROL = 0x0000 |
1232 pCir->chip.lg->ModeReg.DTTC =
1233 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1240 pCir->chip.lg->ModeReg.DTTC =
1241 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1248 pCir->chip.lg->ModeReg.DTTC =
1249 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1256 pCir->chip.lg->ModeReg.DTTC =
1257 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1264 pCir->chip.lg->ModeReg.DTTC =
1265 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1272 pCir->chip.lg->ModeReg.FORMAT = 0x1400;
1275 pCir->chip.lg->ModeReg.FORMAT = 0x1600;
1277 pCir->chip.lg->ModeReg.DTTC =
1278 (pCir->chip.lg->ModeReg.TILE << 8) |
1281 pCir->chip.lg->ModeReg.CONTROL = 0x2000 |
1289 pCir->chip.lg->ModeReg.DTTC =
1290 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1297 pCir->chip.lg->ModeReg.DTTC =
1298 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1305 pCir->chip.lg->ModeReg.DTTC =
1306 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1314 pCir->chip.lg->ModeReg.DTTC =
1315 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1318 pCir->chip.lg->ModeReg.DTTC =
1319 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1323 pCir->chip.lg->ModeReg.FORMAT = 0x2400;
1325 pCir->chip.lg->ModeReg.DTTC =
1326 (pCir->chip.lg->ModeReg.TILE << 8) |
1329 pCir->chip.lg->ModeReg.CONTROL = 0x4000 |
1337 pCir->chip.lg->ModeReg.DTTC =
1338 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1345 pCir->chip.lg->ModeReg.DTTC =
1346 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1354 pCir->chip.lg->ModeReg.DTTC =
1355 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1362 pCir->chip.lg->ModeReg.DTTC =
1363 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1370 pCir->chip.lg->ModeReg.DTTC =
1371 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1375 pCir->chip.lg->ModeReg.FORMAT = 0x3400;
1377 pCir->chip.lg->ModeReg.DTTC =
1378 (pCir->chip.lg->ModeReg.TILE << 8) |
1381 pCir->chip.lg->ModeReg.CONTROL = 0x6000 |
1389 pCir->chip.lg->ModeReg.DTTC =
1390 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1397 pCir->chip.lg->ModeReg.DTTC =
1398 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1406 pCir->chip.lg->ModeReg.DTTC =
1407 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1417 pCir->chip.lg->ModeReg.DTTC =
1418 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1421 pCir->chip.lg->ModeReg.DTTC =
1422 (pCir->chip.lg->ModeReg.DTTC & 0xFFE0) |
1434 pCir->chip.lg->ModeReg.DTTC |= (pCir->chip.lg->memInterleave << 8);
1435 pCir->chip.lg->ModeReg.TILE |= pCir->chip.lg->memInterleave & 0xC0;
1437 if (PCI_CHIP_GD5465 == pCir->Chipset) {
1442 pCir->chip.lg->ModeReg.TileCtrl =
1443 pCir->chip.lg->ModeReg.DTTC & 0xFFC0;
1449 if (pCir->chip.lg->ModeReg.DTTC & 0x0040) {
1454 pCir->chip.lg->ModeReg.DTTC =
1455 (pCir->chip.lg->ModeReg.DTTC & 0xC0FF) |
1456 ((pCir->chip.lg->ModeReg.DTTC & 0x3F00) << 1);
1466 clockData = LgSetClock(pCir, hwp, mode->SynthClock);
1467 pCir->chip.lg->ModeReg.ExtVga[SR0E] = (clockData >> 8) & 0xFF;
1468 pCir->chip.lg->ModeReg.ExtVga[SR1E] = clockData & 0xFF;
1473 LgRestoreLgRegs(pScrn, &pCir->chip.lg->ModeReg);
1516 CirPtr pCir;
1520 pCir = CIRPTR(pScrn);
1546 if (pCir->Chipset == PCI_CHIP_GD5465) {
1552 if (pCir->Chipset == PCI_CHIP_GD5465)
1571 CirPtr pCir;
1578 pCir = CIRPTR(pScrn);
1581 lgReg = &pCir->chip.lg->SavedReg;
1605 CirPtr pCir;
1622 pCir = CIRPTR(pScrn);
1633 if (!CirMapMem(pCir, pScrn->scrnIndex))
1636 lg_vgaHWSetMmioFunc(hwp, pCir->IOBase);
1692 if (pCir->rotate) {
1700 if (pCir->shadowFB) {
1701 pCir->ShadowPitch = BitmapBytePad(pScrn->bitsPerPixel * width);
1702 pCir->ShadowPtr = malloc(pCir->ShadowPitch * height);
1703 displayWidth = pCir->ShadowPitch / (pScrn->bitsPerPixel >> 3);
1704 FbBase = pCir->ShadowPtr;
1706 pCir->ShadowPtr = NULL;
1707 FbBase = pCir->FbBase;
1770 if (!pCir->NoAccel) {
1777 pCir->DGAModeInit = LgModeInit;
1792 if (pCir->HWCursor) {
1809 pScrn->memPhysBase = pCir->FbAddress;
1825 pCir->CloseScreen = pScreen->CloseScreen;
1863 CirPtr pCir = CIRPTR(pScrn);
1868 &LgLineData[pCir->chip.lg->lineDataIndex];
1870 (PCI_CHIP_GD5465 == pCir->Chipset) ?
1876 (PCI_CHIP_GD5465 == pCir->Chipset) ?
1973 CirPtr pCir = CIRPTR(pScrn);
1984 if (pCir->HWCursor)
2004 CirPtr pCir = CIRPTR(pScrn);
2015 if (pCir->HWCursor)
2037 CirPtr pCir = CIRPTR(pScrn);
2041 if (pCir->HWCursor)
2046 CirUnmapMem(pCir, pScrn->scrnIndex);
2050 if (pCir->AccelInfoRec)
2051 XAADestroyInfoRec(pCir->AccelInfoRec);
2052 pCir->AccelInfoRec = NULL;
2055 if (pCir->CursorInfoRec)
2056 xf86DestroyCursorInfoRec(pCir->CursorInfoRec);
2057 pCir->CursorInfoRec = NULL;
2058 if (pCir->DGAModes)
2059 free(pCir->DGAModes);
2060 pCir->DGAnumModes = 0;
2061 pCir->DGAModes = NULL;
2065 pScreen->CloseScreen = pCir->CloseScreen;
2127 CirPtr pCir = CIRPTR(xf86ScreenToScrn(pScreen));
2153 LgSetClock(CirPtr pCir, vgaHWPtr hwp, int freq)
2161 if (!CirrusFindClock(&ffreq, pCir->MaxClock, &num, &den))