Lines Matching refs:low
562 msr_value.low = DF_DEFAULT_XVGA_PAD_SEL_LOW;
569 msr_value.low = mode_params->panel_pad_sel_low;
576 msr_value.low = DF_DEFAULT_TFT_PAD_SEL_LOW;
590 msr_value.low &= ~DF_CONFIG_OUTPUT_MASK;
591 msr_value.low |= DF_OUTPUT_PANEL;
593 msr_value.low |= DF_SIMULTANEOUS_CRT_FP;
595 msr_value.low &= ~DF_SIMULTANEOUS_CRT_FP;
607 msr_value.low &= ~DF_CONFIG_OUTPUT_MASK;
608 msr_value.low |= DF_OUTPUT_PANEL;
610 msr_value.low |= DF_SIMULTANEOUS_CRT_FP;
612 msr_value.low &= ~DF_SIMULTANEOUS_CRT_FP;
619 msr_value.low = DF_DEFAULT_TV_PAD_SEL_LOW;
629 msr_value.low &= ~DF_CONFIG_OUTPUT_MASK;
630 msr_value.low |= DF_OUTPUT_CRT;
691 * latency requirements when setting their power low. Some panels require
892 msr_value.low &= ~(DC3_SPARE_DISABLE_CFIFO_HGO |
904 /* Set aggressive watermarks and disallow forced low priority */
910 msr_value.low |= DC3_SPARE_DISABLE_CFIFO_HGO |
916 * Set average watermarks and allow small regions of forced low
924 msr_value.low |= DC3_SPARE_DISABLE_CFIFO_HGO |
940 * Set low watermarks and allow larger regions of forced low priority
947 msr_value.low |= DC3_SPARE_DISABLE_CFIFO_HGO |
965 msr_value.low |= DC3_SPARE_DISABLE_VFIFO_WM |
1400 current_display->panel_pad_sel_low = msr_value.low;
1472 if (msr_value.low & DF_SIMULTANEOUS_CRT_FP)
1480 if (msr_value.low & GLCP_DOTPLL_HALFPIX)
1733 if ((msr_value.low & GLCP_DOTPLL_LOCK) &&
1734 ((msr_value.low & (GLCP_DOTPLL_HALFPIX | GLCP_DOTPLL_BYPASS)) ==
1744 msr_value.low &= ~(GLCP_DOTPLL_BYPASS | GLCP_DOTPLL_HALFPIX);
1745 msr_value.low |= (pll_low | 0x00000001);
1760 if (msr_value.low & GLCP_DOTPLL_LOCK)
1766 msr_value.low &= 0xFFFFFFFE;
1771 if (!(msr_value.low & GLCP_DOTPLL_LOCK))
2354 msr_value.low |= DC3_SPARE_FIRST_REQ_MASK;
2355 msr_value.low &= ~DC3_SPARE_DISABLE_CWD_CHECK;
2702 if (msr_value.low & GLCP_DOTPLL_HALFPIX)
2704 if (msr_value.low & GLCP_DOTPLL_BYPASS)
2992 msr_value.low = 0;
3007 msr_value.low = 0x00000C00;
3014 msr_value.low = 0x00000A00;
3021 msr_value.low = 0x00000000;
3027 msr_value.low = 0x0000C000;
3032 msr_value.low = 0x0000A000;
3037 msr_value.low = 0x00000A00;
3044 msr_value.low = 0x10800B20;
3051 msr_value.low = 0x10800D20;
3060 msr_value.low = 0x000000A0;
3065 /* Note: VSync low = H3B */
3068 msr_value.low = 0x000000C0;
3075 msr_value.low = 0x00000120;
3083 msr_value.low = 0x00000120;
3090 msr_value.low = 0x00000122;
3099 msr_value.low = 0x10C20120;
3112 msr_value.low = (x - 1) & 0xFFFF;
3114 msr_value.low = x;
3120 msr_value.low += width - 2;
3122 msr_value.low += width - 1;
3127 msr_value.low = y << 16;
3132 msr_value.low += (height - 1) << 16;
3138 msr_value.low = 0x0000FFFF;
3144 msr_value.low = 0xFFFF0000;
3151 msr_value.low = 0xFFFFFFFF;
3158 msr_value.low = 0x000C0000;
3163 msr_value.low = 0x0000000A;
3168 msr_value.low = 0x00C00000;
3174 msr_value.low = 0x0000000A;
3180 * Increment h.counter if xstate = 10 and HSync is low.
3183 msr_value.low = 0x000A00A0;
3185 msr_value.low = 0x00A000A0;
3187 msr_value.low = 0x0A0000A0;
3189 msr_value.low |= 0x0A000000;
3196 msr_value.low = 0x0000000C;
3201 msr_value.low = 0x00000001;
3206 msr_value.low = 0x00000000;
3217 msr_value.low = 0x00000000;
3241 msr_value.low = 5;
3243 msr_value.low = 0;
3245 msr_value.low = 3;
3252 msr_value.low = 0xFFFF0000 | (hactive - 1);
3254 msr_value.low += hblankstart - hactive;
3255 msr_value.low += htotal - hblankend;
3263 msr_value.low = 0x20000FF0;
3270 msr_value.low = 0x002055AA;
3280 msr_value.low = 5;
3282 msr_value.low = 0;
3284 msr_value.low = 2;
3291 msr_value.low = 0xFFFF0000 | (hactive - 1);
3298 msr_value.low = 0xF0000FF0;
3305 msr_value.low = 0x002D55AA;
3317 msr_value.low = 5;
3319 msr_value.low = 0;
3321 msr_value.low = 2;
3330 msr_value.low =
3338 msr_value.low = 0x70000FF0;
3345 msr_value.low = 0x003555AA;
3380 msr_value.low = diag;
3390 msr_value.low = 0x80EA20A0;
3404 if ((msr_value.low & 3) == 3) {
3407 crc = msr_value.low;
3412 msr_value.low = 0x00000000;