Cross Reference: /xsrc/external/mit/xf86-video-geode/dist/src/cim/cim

Lines Matching refs:WRITE_VIP32
132     WRITE_VIP32(VIP_CONTROL1, vip_control1);
133     WRITE_VIP32(VIP_CONTROL2, vip_control2);
134     WRITE_VIP32(VIP_CONTROL3, vip_control3);
173     WRITE_VIP32(VIP_CONTROL3, vip_control3);
174     WRITE_VIP32(VIP_601_HORZ_START, buffer->horz_start);
175     WRITE_VIP32(VIP_601_VBI_START, buffer->vbi_start);
176     WRITE_VIP32(VIP_601_VBI_END, buffer->vbi_start + buffer->vbi_height - 1);
177     WRITE_VIP32(VIP_601_EVEN_START_STOP,
180     WRITE_VIP32(VIP_601_ODD_START_STOP,
183     WRITE_VIP32(VIP_ODD_FIELD_DETECT,
192         WRITE_VIP32(VIP_601_HORZ_END,
195         WRITE_VIP32(VIP_601_HORZ_END, buffer->horz_start + buffer->width + 3);
230         WRITE_VIP32(VIP_TASKA_VID_PITCH,
236             WRITE_VIP32(VIP_TASKA_VID_ODD_BASE, offsets->even_base[cur_buffer]);
237             WRITE_VIP32(VIP_TASKA_VID_EVEN_BASE, offsets->odd_base[cur_buffer]);
239                 WRITE_VIP32(VIP_TASKA_VBI_ODD_BASE, offsets->vbi_even_base);
240                 WRITE_VIP32(VIP_TASKA_VBI_EVEN_BASE, offsets->vbi_odd_base);
244             WRITE_VIP32(VIP_TASKA_VID_ODD_BASE, offsets->odd_base[cur_buffer]);
245             WRITE_VIP32(VIP_TASKA_VID_EVEN_BASE,
248                 WRITE_VIP32(VIP_TASKA_VBI_ODD_BASE, offsets->vbi_odd_base);
249                 WRITE_VIP32(VIP_TASKA_VBI_EVEN_BASE, offsets->vbi_even_base);
256             WRITE_VIP32(VIP_TASKA_U_OFFSET, offsets->odd_uoffset);
257             WRITE_VIP32(VIP_TASKA_V_OFFSET, offsets->odd_voffset);
258             WRITE_VIP32(VIP_TASKA_U_EVEN_OFFSET, offsets->even_uoffset);
259             WRITE_VIP32(VIP_TASKA_V_EVEN_OFFSET, offsets->even_voffset);
267         WRITE_VIP32(VIP_TASKB_VID_PITCH,
273             WRITE_VIP32(VIP_TASKB_VID_ODD_BASE, offsets->even_base[cur_buffer]);
274             WRITE_VIP32(VIP_TASKB_VID_EVEN_BASE, offsets->odd_base[cur_buffer]);
276                 WRITE_VIP32(VIP_TASKB_VBI_ODD_BASE, offsets->vbi_even_base);
277                 WRITE_VIP32(VIP_TASKB_VBI_EVEN_BASE, offsets->vbi_odd_base);
281             WRITE_VIP32(VIP_TASKB_VID_ODD_BASE, offsets->odd_base[cur_buffer]);
282             WRITE_VIP32(VIP_TASKB_VID_EVEN_BASE,
285                 WRITE_VIP32(VIP_TASKB_VBI_ODD_BASE, offsets->vbi_odd_base);
286                 WRITE_VIP32(VIP_TASKB_VBI_EVEN_BASE, offsets->vbi_even_base);
293             WRITE_VIP32(VIP_TASKB_U_OFFSET, offsets->odd_uoffset);
294             WRITE_VIP32(VIP_TASKB_V_OFFSET, offsets->odd_voffset);
298         WRITE_VIP32(VIP_ANC_MSG1_BASE, buffer->ancillaryData.msg1_base);
299         WRITE_VIP32(VIP_ANC_MSG2_BASE, buffer->ancillaryData.msg2_base);
300         WRITE_VIP32(VIP_ANC_MSG_SIZE, buffer->ancillaryData.msg_size);
330             WRITE_VIP32(VIP_TASKA_VID_ODD_BASE, offsets->even_base[cur_buffer]);
331             WRITE_VIP32(VIP_TASKA_VID_EVEN_BASE, offsets->odd_base[cur_buffer]);
334             WRITE_VIP32(VIP_TASKA_VID_ODD_BASE, offsets->odd_base[cur_buffer]);
335             WRITE_VIP32(VIP_TASKA_VID_EVEN_BASE,
345             WRITE_VIP32(VIP_TASKB_VID_ODD_BASE, offsets->even_base[cur_buffer]);
346             WRITE_VIP32(VIP_TASKB_VID_EVEN_BASE, offsets->odd_base[cur_buffer]);
349             WRITE_VIP32(VIP_TASKB_VID_ODD_BASE, offsets->odd_base[cur_buffer]);
350             WRITE_VIP32(VIP_TASKB_VID_EVEN_BASE,
360             WRITE_VIP32(VIP_TASKA_VID_ODD_BASE, offsets->even_base[cur_buffer]);
362             WRITE_VIP32(VIP_TASKA_VID_ODD_BASE, offsets->odd_base[cur_buffer]);
370             WRITE_VIP32(VIP_TASKA_VID_EVEN_BASE, offsets->odd_base[cur_buffer]);
372             WRITE_VIP32(VIP_TASKA_VID_EVEN_BASE,
381             WRITE_VIP32(VIP_TASKB_VID_ODD_BASE, offsets->even_base[cur_buffer]);
383             WRITE_VIP32(VIP_TASKB_VID_ODD_BASE, offsets->odd_base[cur_buffer]);
391             WRITE_VIP32(VIP_TASKB_VID_EVEN_BASE, offsets->odd_base[cur_buffer]);
393             WRITE_VIP32(VIP_TASKB_VID_EVEN_BASE,
421     WRITE_VIP32(VIP_CONTROL1, vip_control1);
430         WRITE_VIP32(VIP_CONTROL1, vip_control1 | VIP_CONTROL1_RESET);
431         WRITE_VIP32(VIP_CONTROL1, vip_control1 & ~VIP_CONTROL1_RESET);
432         WRITE_VIP32(VIP_CONTROL3, vip_control3 | VIP_CONTROL3_FIFO_RESET);
451     WRITE_VIP32(VIP_INTERRUPT, VIP_ALL_INTERRUPTS | (VIP_ALL_INTERRUPTS >> 16));
456     WRITE_VIP32(VIP_CONTROL1, 0);
467     WRITE_VIP32(VIP_CONTROL1, VIP_CONTROL1_RESET);
468     WRITE_VIP32(VIP_CONTROL3, VIP_CONTROL3_FIFO_RESET);
469     WRITE_VIP32(VIP_CONTROL2, 0);
519     WRITE_VIP32(VIP_CONTROL1, vip_control1);
520     WRITE_VIP32(VIP_CONTROL2, vip_control2);
553         WRITE_VIP32(VIP_INTERRUPT, int_enable);
595         WRITE_VIP32(VIP_VSYNC_ERR_COUNT, temp);
600     WRITE_VIP32(VIP_CONTROL2, vip_control2);
624         WRITE_VIP32(VIP_MAX_ADDRESS, max_address & VIP_MAXADDR_MASK);
631     WRITE_VIP32(VIP_CONTROL2, vip_control2);
654     WRITE_VIP32(VIP_CONTROL2, vip_control2);
710     WRITE_VIP32(VIP_CONTROL1, vip_control1);
711     WRITE_VIP32(VIP_CONTROL2, vip_control2);
855     WRITE_VIP32(VIP_CONTROL2, vip_control2);
856     WRITE_VIP32(VIP_PAGE_OFFSET, page_offset);
870     WRITE_VIP32(VIP_CURRENT_TARGET,
893     WRITE_VIP32(VIP_CONTROL1, vip_control1 | VIP_CONTROL1_RESET);
894     WRITE_VIP32(VIP_CONTROL1, vip_control1 & ~VIP_CONTROL1_RESET);
895     WRITE_VIP32(VIP_CONTROL3, vip_control3 | VIP_CONTROL3_FIFO_RESET);
921         WRITE_VIP32(VIP_VERTICAL_START_STOP, ((buffer->stop <<
936     WRITE_VIP32(VIP_CONTROL2, vip_control2);
953     WRITE_VIP32(VIP_INTERRUPT, temp | (interrupt_mask & VIP_ALL_INTERRUPTS));
1037     WRITE_VIP32(VIP_CURRENT_TARGET, restore_buffer->current_target);
1038     WRITE_VIP32(VIP_MAX_ADDRESS, restore_buffer->max_address);
1039     WRITE_VIP32(VIP_TASKA_VID_EVEN_BASE, restore_buffer->taska_evenbase);
1040     WRITE_VIP32(VIP_TASKA_VID_ODD_BASE, restore_buffer->taska_oddbase);
1041     WRITE_VIP32(VIP_TASKA_VBI_EVEN_BASE, restore_buffer->taska_vbi_evenbase);
1042     WRITE_VIP32(VIP_TASKA_VBI_ODD_BASE, restore_buffer->taska_vbi_oddbase);
1043     WRITE_VIP32(VIP_TASKA_VID_PITCH, restore_buffer->taska_data_pitch);
1044     WRITE_VIP32(VIP_CONTROL3, restore_buffer->control3);
1045     WRITE_VIP32(VIP_TASKA_U_OFFSET, restore_buffer->taska_v_oddoffset);
1046     WRITE_VIP32(VIP_TASKA_V_OFFSET, restore_buffer->taska_u_oddoffset);
1047     WRITE_VIP32(VIP_TASKB_VID_EVEN_BASE, restore_buffer->taskb_evenbase);
1048     WRITE_VIP32(VIP_TASKB_VID_ODD_BASE, restore_buffer->taskb_oddbase);
1049     WRITE_VIP32(VIP_TASKB_VBI_EVEN_BASE, restore_buffer->taskb_vbi_evenbase);
1050     WRITE_VIP32(VIP_TASKB_VBI_ODD_BASE, restore_buffer->taskb_vbi_oddbase);
1051     WRITE_VIP32(VIP_TASKB_VID_PITCH, restore_buffer->taskb_pitch);
1052     WRITE_VIP32(VIP_TASKB_U_OFFSET, restore_buffer->taskb_voffset);
1053     WRITE_VIP32(VIP_TASKB_V_OFFSET, restore_buffer->taskb_uoffset);
1054     WRITE_VIP32(VIP_ANC_MSG1_BASE, restore_buffer->msg1_base);
1055     WRITE_VIP32(VIP_ANC_MSG2_BASE, restore_buffer->msg2_base);
1056     WRITE_VIP32(VIP_ANC_MSG_SIZE, restore_buffer->msg_size);
1057     WRITE_VIP32(VIP_PAGE_OFFSET, restore_buffer->page_offset);
1058     WRITE_VIP32(VIP_VERTICAL_START_STOP, restore_buffer->vert_start_stop);
1059     WRITE_VIP32(VIP_VSYNC_ERR_COUNT, restore_buffer->vsync_err_count);
1060     WRITE_VIP32(VIP_TASKA_U_EVEN_OFFSET, restore_buffer->taska_u_evenoffset);
1061     WRITE_VIP32(VIP_TASKA_V_EVEN_OFFSET, restore_buffer->taska_v_evenoffset);
1076     WRITE_VIP32(VIP_CONTROL1, restore_buffer->control1);
1077     WRITE_VIP32(VIP_CONTROL2, restore_buffer->control2);
1078     WRITE_VIP32(VIP_CONTROL3, restore_buffer->control3);
1486     WRITE_VIP32(VIP_FIFO_ADDRESS, dwFifoAddress);
1515     WRITE_VIP32(VIP_FIFO_ADDRESS, dwFifoAddress);
1516     WRITE_VIP32(VIP_FIFO_DATA, dwFifoData);
1544     WRITE_VIP32(VIP_CONTROL2, cw2);