Cross Reference: /xsrc/external/mit/xf86-video-geode/dist/src/gfx/disp

Lines Matching refs:READ_REG32
63         READ_REG32(MDC_UNLOCK);
79         READ_REG32(MDC_UNLOCK);
100         READ_REG32(MDC_DISPLAY_CFG) & ~(MDC_DCFG_DISP_MODE_MASK |
102     lock = READ_REG32(MDC_UNLOCK);
199     unlock = READ_REG32(MDC_UNLOCK);
203     gcfg = READ_REG32(MDC_GENERAL_CFG);
204     dcfg = READ_REG32(MDC_DISPLAY_CFG);
280     temp = READ_REG32(MDC_DV_CTL);
292     vid_buf_size = READ_REG32(MDC_LINE_SIZE) & 0xFF000000;
526     unlock = READ_REG32(MDC_UNLOCK);
530     dcfg = READ_REG32(MDC_DISPLAY_CFG);
531     vactive = READ_REG32(MDC_V_ACTIVE_TIMING);
532     vblank = READ_REG32(MDC_V_BLANK_TIMING);
567     unsigned long lock = READ_REG32(MDC_UNLOCK);
569     value = READ_REG32(MDC_GFX_PITCH) & 0xFFFF0000;
582     value = READ_REG32(MDC_GENERAL_CFG);
612     lock = READ_REG32(MDC_UNLOCK);
660     unlock = READ_REG32(MDC_UNLOCK);
661     dcfg = READ_REG32(MDC_DISPLAY_CFG);
693         unlock = READ_REG32(MDC_UNLOCK);
694         dcfg = READ_REG32(MDC_DISPLAY_CFG);
729     unlock = READ_REG32(MDC_UNLOCK);
730     gcfg = READ_REG32(MDC_GENERAL_CFG);
819     unlock = READ_REG32(MDC_UNLOCK);
928     unlock = READ_REG32(MDC_UNLOCK);
929     gcfg = READ_REG32(MDC_GENERAL_CFG);
980     unsigned long lock = READ_REG32(MDC_UNLOCK);
1040     if (READ_REG32(MDC_FB_ST_OFFSET) & 0x0FFFFFFF)
1051     temp = READ_REG32(MDC_DV_CTL);
1055     unlock = READ_REG32(MDC_UNLOCK);
1056     gcfg = READ_REG32(MDC_GENERAL_CFG);
1081     unlock = READ_REG32(MDC_UNLOCK);
1082     gcfg = READ_REG32(MDC_GENERAL_CFG);
1138     lock = READ_REG32(MDC_UNLOCK);
1162     lock = READ_REG32(MDC_UNLOCK);
1166     line_delta = READ_REG32(MDC_GFX_PITCH) & 0x0000FFFF;
1201     lock = READ_REG32(MDC_UNLOCK);
1202     buf_size = READ_REG32(MDC_LINE_SIZE) & 0xFF80FFFF;
1227     lock = READ_REG32(MDC_UNLOCK);
1228     gcfg = READ_REG32(MDC_GENERAL_CFG);
1267     lock = READ_REG32(MDC_UNLOCK);
1268     gcfg = READ_REG32(MDC_GENERAL_CFG);
1269     dcfg = READ_REG32(MDC_DISPLAY_CFG);
1304     lock = READ_REG32(MDC_UNLOCK);
1305     value = READ_REG32(MDC_LINE_SIZE) & 0x00FFFFFF;
1306     yuv_420 = READ_REG32(MDC_GENERAL_CFG) & MDC_GCFG_YUVM;
1348     lock = READ_REG32(MDC_UNLOCK);
1374     lock = READ_REG32(MDC_UNLOCK);
1404     lock = READ_REG32(MDC_UNLOCK);
1430     lock = READ_REG32(MDC_UNLOCK);
1464     unlock = READ_REG32(MDC_UNLOCK);
1465     gcfg = READ_REG32(MDC_GENERAL_CFG);
1489     if (READ_REG32(MDC_DISPLAY_CFG) & MDC_DCFG_TGEN)
1507     if (READ_REG32(MDC_LINE_CNT_STATUS) & MDC_LNCNT_VNA)
1553     modeBytesPerScanline = (READ_REG32(MDC_GFX_PITCH) & 0x0000FFFF) << 3;
1733     return ((unsigned short) (READ_REG32(MDC_GFX_PITCH) & 0x0000FFFF) << 3);
2119     return ((READ_REG32(MDC_LINE_SIZE) & 0x7FF) << 3);
2134     return ((unsigned short) ((READ_REG32(MDC_H_ACTIVE_TIMING) & 0x0FF8) + 8));
2149     return ((unsigned short) ((READ_REG32(MDC_H_SYNC_TIMING) & 0x0FF8) + 8));
2164     return ((unsigned short) (((READ_REG32(MDC_H_SYNC_TIMING) >> 16) & 0x0FF8)
2180     return ((unsigned short) (((READ_REG32(MDC_H_ACTIVE_TIMING) >> 16) &
2196     return ((unsigned short) ((READ_REG32(MDC_V_ACTIVE_TIMING) & 0x07FF) + 1));
2211     return ((unsigned short) (((READ_REG32(MDC_V_SYNC_TIMING) >> 16) & 0x07FF)
2227     return ((unsigned short) (((READ_REG32(MDC_V_ACTIVE_TIMING) >> 16) &
2245     unsigned long dcfg = READ_REG32(MDC_DISPLAY_CFG);
2287             (unsigned short) (READ_REG32(MDC_LINE_CNT_STATUS) &
2290            (unsigned short) (READ_REG32(MDC_LINE_CNT_STATUS) &
2308     return (READ_REG32(MDC_FB_ST_OFFSET) & 0x0FFFFFFF);
2323     return (READ_REG32(MDC_CURS_ST_OFFSET) & 0x0FFFFFFF);
2344     return ((unsigned short) ((READ_REG32(MDC_H_BLANK_TIMING) & 0x0FF8) + 8));
2359     return ((unsigned short) (((READ_REG32(MDC_H_BLANK_TIMING) >> 16) & 0x0FF8)
2375     return ((unsigned short) ((READ_REG32(MDC_V_BLANK_TIMING) & 0x07FF) + 1));
2390     return ((unsigned short) ((READ_REG32(MDC_V_SYNC_TIMING) & 0x07FF) + 1));
2405     return ((unsigned short) (((READ_REG32(MDC_V_BLANK_TIMING) >> 16) & 0x07FF)
2425     *palette = READ_REG32(MDC_PAL_DATA);
2446         palette[i] = READ_REG32(MDC_PAL_DATA);
2462     return (READ_REG32(MDC_GENERAL_CFG) & MDC_GCFG_CURE);
2477     return ((READ_REG32(MDC_CURSOR_X) & 0x07FF) |
2478             ((READ_REG32(MDC_CURSOR_Y) << 16) & 0x07FF0000));
2493     return (((READ_REG32(MDC_CURSOR_X) >> 11) & 0x03F) |
2494             ((READ_REG32(MDC_CURSOR_Y) << 5) & 0x3F0000));
2515     return READ_REG32(MDC_PAL_DATA);
2530     return (READ_REG32(MDC_GENERAL_CFG) & MDC_GCFG_ICNE);
2545     return (READ_REG32(MDC_ICON_ST_OFFSET) & 0x0FFFFFFF);
2560     return (READ_REG32(MDC_ICON_X) & 0x07FF);
2580     return READ_REG32(MDC_PAL_DATA);
2595     if (READ_REG32(MDC_GENERAL_CFG) & MDC_GCFG_CMPE)
2613     return (READ_REG32(MDC_CB_ST_OFFSET) & 0x007FFFFF);
2630     pitch = (unsigned short) (READ_REG32(MDC_GFX_PITCH) >> 16);
2648     size = (unsigned short) ((READ_REG32(MDC_LINE_SIZE) >> 16) & 0x7F) - 1;
2667     offset = READ_REG32(MDC_PHY_MEM_OFFSET) & 0xFF000000;
2671     valid = (int) READ_REG32(MDC_DV_ACC) & 2;
2693     return (READ_REG32(MDC_VID_Y_ST_OFFSET) & 0x0FFFFFFF);
2715     *yoffset = (READ_REG32(MDC_VID_Y_ST_OFFSET) & 0x0FFFFFFF);
2716     *uoffset = (READ_REG32(MDC_VID_U_ST_OFFSET) & 0x0FFFFFFF);
2717     *voffset = (READ_REG32(MDC_VID_V_ST_OFFSET) & 0x0FFFFFFF);
2735     unsigned long pitch = READ_REG32(MDC_VID_YUV_PITCH);
2756     return (READ_REG32(MDC_VID_DS_DELTA) >> 18);
2775     return ((int) ((READ_REG32(MDC_GENERAL_CFG) >> 19) & 1));
2795     return ((READ_REG32(MDC_LINE_SIZE) >> 21) & 0x000007FF);