Cross Reference: /xsrc/external/mit/xf86-video-i128/dist/src/i128accel.c

Lines Matching refs:rbase_a
67 #define ENG_PIPELINE_READY() { while (pI128->mem.rbase_a[BUSY] & BUSY_BUSY) ; }
68 #define ENG_DONE() { while (pI128->mem.rbase_a[FLOW] & (FLOW_DEB | FLOW_MCB | FLOW_PRV)) ;}
120 	pI128->mem.rbase_a[CMD] = pI128->cmd;
121 	/*pI128->mem.rbase_a[XY3_DIR] = pI128->blitdir;*/
143 		bppi = (pI128->mem.rbase_a[BUF_CTRL] & BC_PSIZ_MSK) >> 24;
156 			pI128->mem.rbase_a[XY2_WH] = (bppi<<16) | h;
157 			pI128->mem.rbase_a[XY0_SRC] = (x1<<16) | y1;	MB;
158 			pI128->mem.rbase_a[XY1_DST] = (x2<<16) | y2;	MB;
175 			pI128->mem.rbase_a[CLPTL] = (x2<<16) | y2;
176 			pI128->mem.rbase_a[CLPBR] = ((x2+w)<<16) | (y2+h);
182 	pI128->mem.rbase_a[XY2_WH] = (w<<16) | h;
183 	pI128->mem.rbase_a[XY0_SRC] = (x1<<16) | y1;			MB;
184 	pI128->mem.rbase_a[XY1_DST] = (x2<<16) | y2;			MB;
201 		pI128->mem.rbase_a[MASK] = -1;
204 			pI128->mem.rbase_a[MASK] = planemask |
210 			pI128->mem.rbase_a[MASK] = planemask | (planemask<<16);
215 			pI128->mem.rbase_a[MASK] = planemask;
220 	pI128->mem.rbase_a[CLPTL] = 0x00000000;
221 	pI128->mem.rbase_a[CLPBR] = (4095<<16) | 2047;
224 		pI128->mem.rbase_a[BACK] = transparency_color;
234 	pI128->mem.rbase_a[XY3_DIR] = pI128->blitdir;
239 	pI128->mem.rbase_a[CMD] = pI128->cmd;
262 		pI128->mem.rbase_a[MASK] = -1;
265 			pI128->mem.rbase_a[MASK] = planemask |
271 			pI128->mem.rbase_a[MASK] = planemask | (planemask<<16);
276 			pI128->mem.rbase_a[MASK] = planemask;
280 	pI128->mem.rbase_a[FORE] = color;
282 	pI128->clptl = pI128->mem.rbase_a[CLPTL] = 0x00000000;
283 	pI128->clpbr = pI128->mem.rbase_a[CLPBR] = (4095<<16) | 2047 ;
285 	pI128->mem.rbase_a[XY3_DIR] = pI128->blitdir = DIR_LR_TB;
289 	pI128->mem.rbase_a[CMD] = pI128->cmd;
317 	pI128->mem.rbase_a[CMD] =
324 	pI128->mem.rbase_a[CLPTL] = pI128->clptl;
325 	pI128->mem.rbase_a[CLPBR] = pI128->clpbr;
327 	pI128->mem.rbase_a[XY0_SRC] = (x1<<16) | y1;			MB;
328 	pI128->mem.rbase_a[XY1_DST] = (x2<<16) | y2;			MB;
373 	pI128->mem.rbase_a[MASK] = planemask;
374 	pI128->mem.rbase_a[FORE] = fg;
375 	pI128->mem.rbase_a[CMD] = (CS_SOLID<<16) | i128alu[rop] | CO_BITBLT;
376 	pI128->mem.rbase_a[CLPTL] = 0x00000000;
377 	pI128->mem.rbase_a[CLPBR] = (4095<<16) | 2047;
379 	pI128->mem.rbase_a[XY3_DIR] = DIR_LR_TB;
380 	pI128->mem.rbase_a[XY0_SRC] = 0x00000000;
386 			pI128->mem.rbase_a[XY2_WH] = (w<<16) | h;	MB;
387 			pI128->mem.rbase_a[XY1_DST] =
501 	pI128->mem.rbase_a[BUF_CTRL] = buf_ctrl;
503 	pI128->mem.rbase_a[DE_PGE] = 0x00;
504 	pI128->mem.rbase_a[DE_SORG] = pI128->displayOffset;
505 	pI128->mem.rbase_a[DE_DORG] = pI128->displayOffset;
506 	pI128->mem.rbase_a[DE_MSRC] = 0x00;
507 	pI128->mem.rbase_a[DE_WKEY] = 0x00;
508 	pI128->mem.rbase_a[DE_SPTCH] = pI128->mem.rbase_g[DB_PTCH];
509 	pI128->mem.rbase_a[DE_DPTCH] = pI128->mem.rbase_g[DB_PTCH];
511 		pI128->mem.rbase_a[DE_ZPTCH] = pI128->mem.rbase_g[DB_PTCH];
512 	pI128->mem.rbase_a[RMSK] = 0x00000000;
513 	pI128->mem.rbase_a[XY4_ZM] = ZOOM_NONE;
514 	pI128->mem.rbase_a[LPAT] = 0xffffffff;  /* for lines */
515 	pI128->mem.rbase_a[PCTRL] = 0x00000000; /* for lines */
516 	pI128->mem.rbase_a[CLPTL] = 0x00000000;
517 	pI128->mem.rbase_a[CLPBR] = (4095<<16) | 2047 ;
520 		pI128->mem.rbase_a[ACNTRL] = 0x00000000;
521 	pI128->mem.rbase_a[INTM] = 0x03;