Lines Matching refs:INDEX_TI
94 pI128->mem.rbase_g[INDEX_TI] = TI_CURS_CONTROL; MB;
96 pI128->mem.rbase_g[INDEX_TI] = TI_TRUE_COLOR_CONTROL; MB;
98 pI128->mem.rbase_g[INDEX_TI] = TI_VGA_SWITCH_CONTROL; MB;
100 pI128->mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_1; MB;
102 pI128->mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_2; MB;
104 pI128->mem.rbase_g[INDEX_TI] = TI_INPUT_CLOCK_SELECT; MB;
106 pI128->mem.rbase_g[INDEX_TI] = TI_OUTPUT_CLOCK_SELECT; MB;
108 pI128->mem.rbase_g[INDEX_TI] = TI_PALETTE_PAGE; MB;
110 pI128->mem.rbase_g[INDEX_TI] = TI_GENERAL_CONTROL; MB;
112 pI128->mem.rbase_g[INDEX_TI] = TI_MISC_CONTROL; MB;
114 pI128->mem.rbase_g[INDEX_TI] = TI_AUXILIARY_CONTROL; MB;
116 pI128->mem.rbase_g[INDEX_TI] = TI_GENERAL_IO_CONTROL; MB;
118 pI128->mem.rbase_g[INDEX_TI] = TI_GENERAL_IO_DATA; MB;
120 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_DCLK_CONTROL; MB;
122 pI128->mem.rbase_g[INDEX_TI] = TI_COLOR_KEY_CONTROL; MB;
125 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
127 pI128->mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB;
130 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
132 pI128->mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB;
135 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
137 pI128->mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB;
140 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
142 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB;
145 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
147 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB;
150 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
152 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB;
155 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
157 pI128->mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB;
160 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
162 pI128->mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB;
165 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
167 pI128->mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB;
198 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
200 pI128->mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB;
203 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
205 pI128->mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB;
208 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
210 pI128->mem.rbase_g[INDEX_TI] = TI_PIXEL_CLOCK_PLL_DATA; MB;
213 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
215 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB;
218 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
220 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB;
223 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
225 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_PLL_DATA; MB;
228 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
230 pI128->mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB;
233 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
235 pI128->mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB;
238 pI128->mem.rbase_g[INDEX_TI] = TI_PLL_CONTROL; MB;
240 pI128->mem.rbase_g[INDEX_TI] = TI_LOOP_CLOCK_PLL_DATA; MB;
243 pI128->mem.rbase_g[INDEX_TI] = TI_CURS_CONTROL; MB;
245 pI128->mem.rbase_g[INDEX_TI] = TI_TRUE_COLOR_CONTROL; MB;
247 pI128->mem.rbase_g[INDEX_TI] = TI_VGA_SWITCH_CONTROL; MB;
249 pI128->mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_1; MB;
251 pI128->mem.rbase_g[INDEX_TI] = TI_MUX_CONTROL_2; MB;
253 pI128->mem.rbase_g[INDEX_TI] = TI_INPUT_CLOCK_SELECT; MB;
255 pI128->mem.rbase_g[INDEX_TI] = TI_OUTPUT_CLOCK_SELECT; MB;
257 pI128->mem.rbase_g[INDEX_TI] = TI_PALETTE_PAGE; MB;
259 pI128->mem.rbase_g[INDEX_TI] = TI_GENERAL_CONTROL; MB;
261 pI128->mem.rbase_g[INDEX_TI] = TI_MISC_CONTROL; MB;
263 pI128->mem.rbase_g[INDEX_TI] = TI_AUXILIARY_CONTROL; MB;
265 pI128->mem.rbase_g[INDEX_TI] = TI_GENERAL_IO_CONTROL; MB;
267 pI128->mem.rbase_g[INDEX_TI] = TI_GENERAL_IO_DATA; MB;
269 pI128->mem.rbase_g[INDEX_TI] = TI_MCLK_DCLK_CONTROL; MB;
271 pI128->mem.rbase_g[INDEX_TI] = TI_COLOR_KEY_CONTROL; MB;