Lines Matching refs:i810Reg
730 DoSave(ScrnInfoPtr scrn, vgaRegPtr vgaReg, I810RegPtr i810Reg,
753 i810Reg->IOControl = hwp->readCrtc(hwp, IO_CTNL);
754 i810Reg->AddressMapping = hwp->readGr(hwp, ADDRESS_MAPPING);
755 i810Reg->BitBLTControl = INREG8(BITBLT_CNTL);
756 i810Reg->VideoClk2_M = INREG16(VCLK2_VCO_M);
757 i810Reg->VideoClk2_N = INREG16(VCLK2_VCO_N);
758 i810Reg->VideoClk2_DivisorSel = INREG8(VCLK2_VCO_DIV_SEL);
760 i810Reg->ExtVertTotal = hwp->readCrtc(hwp, EXT_VERT_TOTAL);
761 i810Reg->ExtVertDispEnd = hwp->readCrtc(hwp, EXT_VERT_DISPLAY);
762 i810Reg->ExtVertSyncStart = hwp->readCrtc(hwp, EXT_VERT_SYNC_START);
763 i810Reg->ExtVertBlankStart = hwp->readCrtc(hwp, EXT_VERT_BLANK_START);
764 i810Reg->ExtHorizTotal = hwp->readCrtc(hwp, EXT_HORIZ_TOTAL);
765 i810Reg->ExtHorizBlank = hwp->readCrtc(hwp, EXT_HORIZ_BLANK);
766 i810Reg->ExtOffset = hwp->readCrtc(hwp, EXT_OFFSET);
767 i810Reg->InterlaceControl = hwp->readCrtc(hwp, INTERLACE_CNTL);
769 i810Reg->PixelPipeCfg0 = INREG8(PIXPIPE_CONFIG_0);
770 i810Reg->PixelPipeCfg1 = INREG8(PIXPIPE_CONFIG_1);
771 i810Reg->PixelPipeCfg2 = INREG8(PIXPIPE_CONFIG_2);
772 i810Reg->DisplayControl = INREG8(DISPLAY_CNTL);
773 i810Reg->LMI_FIFO_Watermark = INREG(FWATER_BLC);
776 i810Reg->Fence[i] = INREG(FENCE + i * 4);
778 i810Reg->LprbTail = INREG(LP_RING + RING_TAIL);
779 i810Reg->LprbHead = INREG(LP_RING + RING_HEAD);
780 i810Reg->LprbStart = INREG(LP_RING + RING_START);
781 i810Reg->LprbLen = INREG(LP_RING + RING_LEN);
783 if ((i810Reg->LprbTail & TAIL_ADDR) != (i810Reg->LprbHead & HEAD_ADDR) &&
784 i810Reg->LprbLen & RING_VALID) {
871 DoRestore(ScrnInfoPtr scrn, vgaRegPtr vgaReg, I810RegPtr i810Reg,
885 i810PrintMode(vgaReg, i810Reg);
901 OUTREG16(VCLK2_VCO_M, i810Reg->VideoClk2_M);
902 OUTREG16(VCLK2_VCO_N, i810Reg->VideoClk2_N);
903 OUTREG8(VCLK2_VCO_DIV_SEL, i810Reg->VideoClk2_DivisorSel);
916 temp |= (i810Reg->PixelPipeCfg0 & DAC_8_BIT);
928 * if (i810Reg->std.NoClock >= 0)
936 hwp->writeCrtc(hwp, EXT_VERT_TOTAL, i810Reg->ExtVertTotal);
937 hwp->writeCrtc(hwp, EXT_VERT_DISPLAY, i810Reg->ExtVertDispEnd);
938 hwp->writeCrtc(hwp, EXT_VERT_SYNC_START, i810Reg->ExtVertSyncStart);
939 hwp->writeCrtc(hwp, EXT_VERT_BLANK_START, i810Reg->ExtVertBlankStart);
940 hwp->writeCrtc(hwp, EXT_HORIZ_TOTAL, i810Reg->ExtHorizTotal);
941 hwp->writeCrtc(hwp, EXT_HORIZ_BLANK, i810Reg->ExtHorizBlank);
942 hwp->writeCrtc(hwp, EXT_OFFSET, i810Reg->ExtOffset);
946 temp |= i810Reg->InterlaceControl;
951 temp |= i810Reg->AddressMapping;
966 ActiveStart = i810Reg->OverlayActiveStart;
967 ActiveEnd = i810Reg->OverlayActiveEnd;
981 temp |= i810Reg->BitBLTControl;
986 temp |= i810Reg->DisplayControl;
991 temp |= i810Reg->PixelPipeCfg0;
996 temp |= i810Reg->PixelPipeCfg2;
1002 temp |= i810Reg->PixelPipeCfg1;
1010 itemp |= i810Reg->LMI_FIFO_Watermark;
1014 OUTREG(FENCE + i * 4, i810Reg->Fence[i]);
1016 ErrorF("Fence Register : %x\n", i810Reg->Fence[i]);
1036 itemp |= i810Reg->LprbStart;
1041 itemp |= i810Reg->LprbLen;
1057 temp |= i810Reg->IOControl;
1110 I810RegPtr i810Reg = &pI810->ModeReg;
1150 i810Reg->VideoClk2_M = (m_best - 2) & 0x3FF;
1151 i810Reg->VideoClk2_N = (n_best - 2) & 0x3FF;
1152 i810Reg->VideoClk2_DivisorSel = (p_best << 4);
1157 i810Reg->VideoClk2_M, i810Reg->VideoClk2_N,
1158 i810Reg->VideoClk2_DivisorSel, m_best, n_best, p_best);
1165 I810RegPtr i810Reg = &pI810->ModeReg;
1172 i810Reg->ExtOffset = scrn->displayWidth >> 11;
1173 i810Reg->PixelPipeCfg1 = DISPLAY_8BPP_MODE;
1174 i810Reg->BitBLTControl = COLEXP_8BPP;
1178 i810Reg->PixelPipeCfg1 = DISPLAY_15BPP_MODE;
1180 i810Reg->PixelPipeCfg1 = DISPLAY_16BPP_MODE;
1183 i810Reg->ExtOffset = scrn->displayWidth >> 10;
1184 i810Reg->BitBLTControl = COLEXP_16BPP;
1187 i810Reg->PixelPipeCfg2 = DISPLAY_GAMMA_ENABLE;
1191 i810Reg->ExtOffset = (scrn->displayWidth * 3) >> 11;
1193 i810Reg->PixelPipeCfg1 = DISPLAY_24BPP_MODE;
1194 i810Reg->BitBLTControl = COLEXP_24BPP;
1197 i810Reg->PixelPipeCfg2 = DISPLAY_GAMMA_ENABLE;
1205 i810Reg->PixelPipeCfg0 = DAC_6_BIT;
1207 i810Reg->PixelPipeCfg0 = DAC_8_BIT;
1210 i810Reg->PixelPipeCfg1 |= 0x10;
1213 i810Reg->IOControl = EXTENDED_CRTC_CNTL;
1216 i810Reg->AddressMapping = (LINEAR_MODE_ENABLE | GTT_MEM_MAP_ENABLE);
1219 i810Reg->DisplayControl = HIRES_MODE;
1222 i810Reg->ExtVertTotal = (mode->CrtcVTotal - 2) >> 8;
1223 i810Reg->ExtVertDispEnd = (mode->CrtcVDisplay - 1) >> 8;
1224 i810Reg->ExtVertSyncStart = mode->CrtcVSyncStart >> 8;
1225 i810Reg->ExtVertBlankStart = mode->CrtcVBlankStart >> 8;
1226 i810Reg->ExtHorizTotal = ((mode->CrtcHTotal >> 3) - 5) >> 8;
1227 i810Reg->ExtHorizBlank = (((mode->CrtcHBlankEnd >> 3) - 1) & 0x40) >> 6;
1241 i810Reg->ExtHorizBlank = vgaHWHBlankKGA(mode, pVga, 7, 0);
1248 if ((mode->CrtcVDisplay == 768) && (i810Reg->ExtVertBlankStart == 3)) {
1249 i810Reg->ExtVertBlankStart = 2;
1251 if ((mode->CrtcVDisplay == 1024) && (i810Reg->ExtVertBlankStart == 4)) {
1252 i810Reg->ExtVertBlankStart = 3;
1256 i810Reg->OverlayActiveStart = mode->CrtcHTotal - 32;
1257 i810Reg->OverlayActiveEnd = mode->CrtcHDisplay - 32;
1261 i810Reg->InterlaceControl = INTERLACE_ENABLE;
1262 i810Reg->ExtVertDispEnd *= 2;
1264 i810Reg->InterlaceControl = INTERLACE_DISABLE;
1282 i810Reg->LMI_FIFO_Watermark = I810CalcWatermark(scrn, dclk, FALSE);
1285 i810Reg->LprbTail = 0;
1286 i810Reg->LprbHead = 0;
1287 i810Reg->LprbStart = pI810->LpRing->mem.Start;
1289 if (i810Reg->LprbStart)
1290 i810Reg->LprbLen = ((pI810->LpRing->mem.Size - 4096) |
1293 i810Reg->LprbLen = RING_INVALID;
1565 I810RegPtr i810Reg = &pI810->ModeReg;
1569 i810Reg->Fence[i] = 0;