Lines Matching defs:OUT_BATCH
177 #define OUT_BATCH(v) batch_emit(sna, v)
224 OUT_BATCH(GEN5_3DPRIMITIVE |
229 OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start);
230 OUT_BATCH(sna->render.vertex_start);
231 OUT_BATCH(1); /* single instance */
232 OUT_BATCH(0); /* start instance location */
233 OUT_BATCH(0); /* index buffer offset, ignored */
548 OUT_BATCH(GEN5_3DSTATE_VERTEX_BUFFERS | 3);
549 OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT | VB0_VERTEXDATA |
553 OUT_BATCH(0);
554 OUT_BATCH(~0); /* max address: disabled */
555 OUT_BATCH(0);
567 OUT_BATCH(GEN5_3DPRIMITIVE |
573 OUT_BATCH(0); /* vertex count, to be filled in later */
574 OUT_BATCH(sna->render.vertex_index);
575 OUT_BATCH(1); /* single instance */
576 OUT_BATCH(0); /* start instance location */
577 OUT_BATCH(0); /* index buffer offset, ignored */
713 OUT_BATCH(GEN5_URB_FENCE |
720 OUT_BATCH(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
723 OUT_BATCH(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
727 OUT_BATCH(GEN5_CS_URB_STATE | 0);
728 OUT_BATCH((URB_CS_ENTRY_SIZE - 1) << 4 | URB_CS_ENTRIES << 0);
735 OUT_BATCH(GEN5_STATE_BASE_ADDRESS | 6);
736 OUT_BATCH(kgem_add_reloc(&sna->kgem, /* general */
741 OUT_BATCH(kgem_add_reloc(&sna->kgem, /* surface */
746 OUT_BATCH(0); /* media */
747 OUT_BATCH(kgem_add_reloc(&sna->kgem, /* instruction */
754 OUT_BATCH(BASE_ADDRESS_MODIFY);
755 OUT_BATCH(0);
756 OUT_BATCH(BASE_ADDRESS_MODIFY);
772 OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
774 OUT_BATCH(GEN5_PIPELINE_SELECT | PIPELINE_SELECT_3D);
821 OUT_BATCH(GEN5_3DSTATE_BINDING_TABLE_POINTERS | 4);
822 OUT_BATCH(0); /* vs */
823 OUT_BATCH(0); /* gs */
824 OUT_BATCH(0); /* clip */
825 OUT_BATCH(0); /* sf */
827 OUT_BATCH(offset*4);
858 OUT_BATCH(GEN5_3DSTATE_PIPELINED_POINTERS | 5);
859 OUT_BATCH(sna->render_state.gen5.vs);
860 OUT_BATCH(GEN5_GS_DISABLE); /* passthrough */
861 OUT_BATCH(GEN5_CLIP_DISABLE); /* passthrough */
862 OUT_BATCH(sna->render_state.gen5.sf[op->mask.bo != NULL]);
863 OUT_BATCH(sna->render_state.gen5.wm + sp);
864 OUT_BATCH(sna->render_state.gen5.cc + bp);
891 OUT_BATCH(GEN5_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
892 OUT_BATCH(0x00000000);
893 OUT_BATCH(limit);
894 OUT_BATCH(offset);
927 OUT_BATCH(GEN5_3DSTATE_VERTEX_ELEMENTS |
930 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
933 OUT_BATCH((VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) |
939 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
942 OUT_BATCH(VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
979 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
981 OUT_BATCH(dw);
1011 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
1013 OUT_BATCH(dw);
1021 OUT_BATCH(GEN5_PIPE_CONTROL |
1024 OUT_BATCH(0);
1025 OUT_BATCH(0);
1026 OUT_BATCH(0);
1028 OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
1056 OUT_BATCH(MI_FLUSH);
Indexes created Sun Jul 05 00:25:41 UTC 2026