Cross Reference: /xsrc/external/mit/xf86-video-intel-old/dist/src/i830

Lines Matching refs:XNFprintf
53     return XNFprintf("0x%04x", (uint16_t)val);
77     return XNFprintf("%s, XOR randomization: %sabled, XOR bit: %d",
94     return XNFprintf("%s, ch2 enh %sabled, ch1 enh %sabled, ch0 enh %sabled, "
106     return XNFprintf("%d, %d", (val & 0xffff) + 1,
112     return XNFprintf("%d, %d", ((val & 0xffff0000) >> 16) + 1,
118     return XNFprintf("%d, %d", (val & 0xffff),
124     return XNFprintf("%d bytes", val);
132 	return XNFprintf("%s", enabled);
134 	return XNFprintf("%s, pipe %c", enabled, plane);
164 	return XNFprintf("%s, %s, %s", enabled, bit30, bpc);
166 	return XNFprintf("%s, %s", enabled, bit30);
196     return XNFprintf("status:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
226     return XNFprintf("%d active, %d total", (val & 0xffff) + 1,
232     return XNFprintf("%d start, %d end", (val & 0xffff) + 1,
238     return XNFprintf("%s", val & VGA_DISP_DISABLE ? "disabled" : "enabled");
244 	return XNFprintf("n = %d, m1 = %d, m2 = %d",
249     return XNFprintf("n = %d, m1 = %d, m2 = %d",
273     return XNFprintf("vga0 p1 = %d, p2 = %d, vga1 p1 = %d, p2 = %d",
295     return XNFprintf("%s, %s, sequencing %s", status, ready, seq);
300     return XNFprintf("power target: %s",
385     return XNFprintf("%s, %s%s, %s clock, %s mode, p1 = %d, "
402     return XNFprintf("%s%s%s%s%s%s",
415 	return XNFprintf("%s, transcoder %c, %chsync, %cvsync",
418 	return XNFprintf("%s, pipe %c, %chsync, %cvsync",
439     return XNFprintf("%s, pipe %c, %d bit, %s",
466     return XNFprintf("%s, pipe %c, %s, %chsync, %cvsync",
487     return XNFprintf("%s, pipe %c, stall %s, %sdetected%s%s",
526     return XNFprintf ("clock gates disabled:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
576     return XNFprintf("%s, %c tiled, %4d pitch, 0x%08x - 0x%08x (%dkb)",
590     return XNFprintf("%s, %c tile walk, %4d pitch, 0x%08x start",
601     return XNFprintf("                                   0x%08x end", end);
876     return XNFprintf("low %d, high %d", val & RR_HW_LOW_POWER_FRAMES_MASK,
882     return XNFprintf("TU %d, val 0x%x %d", (val >> 25) + 1, val & 0xffffff, val & 0xffffff);
887     return XNFprintf("val 0x%x %d", val & 0xffffff, val & 0xffffff);
958     return XNFprintf("%s, train pattern %s, voltage swing %s,"
1017     return XNFprintf("%s, train pattern %s, port width %s, %s,"
1037     return XNFprintf("%d", val >> 6);
1086     return XNFprintf("%s, sdvo high speed %s, mode %s, p2 %s, "
1114     return XNFprintf("cpu source %s, ssc_source %s, nonspread_source %s, "
1152     return XNFprintf("FDL_TP1 timer %s, FDL_TP2 timer %s, freq %d",
1159     return XNFprintf("FDI Delay %d", val & ((1 << 13) - 1));
1164     return XNFprintf("%s, %s",
1203     return XNFprintf("%s, auto_scale %s, auto_scale_cal %s, v_filter %s, vadapt %s, mode %s, filter_sel %s,"
1223     return XNFprintf("%d, %d", a, b);