Lines Matching refs:dpll
1520 uint32_t dpll = 0, fp = 0, dspcntr, pipeconf, lvds_bits = 0;
1619 dpll = DPLL_VGA_MODE_DIS;
1622 dpll |= DPLLB_MODE_LVDS;
1624 dpll |= DPLLB_MODE_DAC_SERIAL;
1627 dpll |= DPLL_DVO_HIGH_SPEED;
1631 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
1637 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
1639 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1642 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1645 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1648 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1651 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1655 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
1658 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1661 dpll |= PLL_P1_DIVIDE_BY_TWO;
1663 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1665 dpll |= PLL_P2_DIVIDE_BY_4;
1670 dpll |= PLL_REF_INPUT_TVCLKINBC;
1674 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
1675 dpll |= 3;
1678 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1680 dpll |= PLL_REF_INPUT_DREFCLK;
1732 dpll |= DPLL_VCO_ENABLE;
1751 if (dpll & DPLL_VCO_ENABLE)
1754 OUTREG(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
1808 OUTREG(dpll_reg, dpll);
1819 OUTREG(dpll_reg, dpll);
2200 uint32_t dpll = INREG((pipe == 0) ? DPLL_A : DPLL_B);
2204 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
2219 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
2222 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
2225 switch (dpll & DPLL_MODE_MASK) {
2227 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10;
2230 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 7 : 14;
2235 (int)(dpll & DPLL_MODE_MASK));
2239 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
2247 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
2256 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
2261 if (dpll & PLL_P1_DIVIDE_BY_TWO) {
2264 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
2267 if (dpll & PLL_P2_DIVIDE_BY_4)