Lines Matching refs:refclk
459 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
461 static void i8xx_clock(int refclk, intel_clock_t *clock)
465 clock->vco = refclk * clock->m / (clock->n + 2);
469 /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */
471 static void i9xx_clock(int refclk, intel_clock_t *clock)
475 clock->vco = refclk * clock->m / (clock->n + 2);
480 static void igd_clock(int refclk, intel_clock_t *clock)
484 clock->vco = refclk * clock->m / clock->n;
488 static void intel_clock(I830Ptr pI830, int refclk, intel_clock_t *clock)
492 igd_clock(refclk, clock);
494 i9xx_clock (refclk, clock);
496 i8xx_clock (refclk, clock);
536 * Returns whether the given set of divisors are valid for a given refclk with
574 int target, int refclk, intel_clock_t *best_clock)
613 intel_clock (pI830, refclk, &clock);
632 int target, int refclk, intel_clock_t *best_clock)
670 intel_clock (pI830, refclk, &clock);
1518 int refclk;
1567 refclk = pI830->lvds_ssc_freq * 1000;
1569 "using SSC reference clock of %d MHz\n", refclk / 1000);
1571 refclk = 96000;
1573 refclk = 48000;
1578 * refclk, or FALSE. The returned values represent the clock equation:
1582 ok = limit->find_pll(limit, crtc, adjusted_mode->Clock, refclk, &clock);