Cross Reference: /xsrc/external/mit/xf86-video-intel-old/dist/src/i965

Lines Matching refs:sf_state
632     struct brw_sf_unit_state *sf_state;
636 				     sizeof(*sf_state), 4096);
638     sf_state = sf_state_bo->virtual;
640     memset(sf_state, 0, sizeof(*sf_state));
641     sf_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
642     sf_state->thread0.kernel_start_pointer =
645 			 kernel_bo, sf_state->thread0.grf_reg_count << 1,
647     sf_state->sf1.single_program_flow = 1;
648     sf_state->sf1.binding_table_entry_count = 0;
649     sf_state->sf1.thread_priority = 0;
650     sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
651     sf_state->sf1.illegal_op_exception_enable = 1;
652     sf_state->sf1.mask_stack_exception_enable = 1;
653     sf_state->sf1.sw_exception_enable = 1;
654     sf_state->thread2.per_thread_scratch_space = 0;
656     sf_state->thread2.scratch_space_base_pointer = 0;
657     sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
658     sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
659     sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
661     sf_state->thread3.urb_entry_read_offset = 1;
662     sf_state->thread3.dispatch_grf_start_reg = 3;
663     sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
664     sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
665     sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
666     sf_state->thread4.stats_enable = 1;
667     sf_state->sf5.viewport_transform = FALSE; /* skip viewport */
668     sf_state->sf6.cull_mode = BRW_CULLMODE_NONE;
669     sf_state->sf6.scissor = 0;
670     sf_state->sf7.trifan_pv = 2;
671     sf_state->sf6.dest_org_vbias = 0x8;
672     sf_state->sf6.dest_org_hbias = 0x8;