Cross Reference: /xsrc/external/mit/xf86-video-intel/dist/src/sna/gen3

Lines Matching refs:dest_mask
1236 #define gen3_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2)	\
1237 	_gen3_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2)
1242 #define _gen3_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \
1248 			  (((dest_mask) & ~MASK_SATURATE) << A0_DEST_CHANNEL_SHIFT) | \
1249 			  (((dest_mask) & MASK_SATURATE) ? A0_DEST_SATURATE : 0) | \
1356 #define gen3_fs_mov_masked(dest_reg, dest_mask, operand0)		\
1357 	gen3_fs_arith_masked (MOV, dest_reg, dest_mask, \
1382 #define gen3_fs_rcp(dest_reg, dest_mask, operand0)		\
1384 		if (dest_mask) {							\
1385 			gen3_fs_arith_masked (RCP, dest_reg, dest_mask, \
1398 #define gen3_fs_rsq(dest_reg, dest_mask, operand0)		\
1400 		if (dest_mask) {							\
1401 			gen3_fs_arith_masked (RSQ, dest_reg, dest_mask, \
1429 #define gen3_fs_mad(dest_reg, dest_mask, op0, op1, op2)	\
1431 		if (dest_mask) {							\
1432 			gen3_fs_arith_masked (MAD, dest_reg, dest_mask, op0, op1, op2); \
1438 #define gen3_fs_dp2add(dest_reg, dest_mask, op0, op1, op2)	\
1440 		if (dest_mask) {							\
1441 			gen3_fs_arith_masked (DP2ADD, dest_reg, dest_mask, op0, op1, op2); \
1449  * resulting scalar in the channels of dest_reg specified by the dest_mask.
1451 #define gen3_fs_dp3(dest_reg, dest_mask, op0, op1)	\
1453 		if (dest_mask) {							\
1454 			gen3_fs_arith_masked (DP3, dest_reg, dest_mask, \
1465  * resulting scalar in the channels of dest_reg specified by the dest_mask.
1467 #define gen3_fs_dp4(dest_reg, dest_mask, op0, op1)	\
1469 		if (dest_mask) {							\
1470 			gen3_fs_arith_masked (DP4, dest_reg, dest_mask, \