Cross Reference: /xsrc/external/mit/xf86-video-intel/dist/src/sna/gen5

Lines Matching defs:OUT_BATCH
214 #define OUT_BATCH(v) batch_emit(sna, v)
261 	OUT_BATCH(GEN5_3DPRIMITIVE |
266 	OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start);
267 	OUT_BATCH(sna->render.vertex_start);
268 	OUT_BATCH(1);	/* single instance */
269 	OUT_BATCH(0);	/* start instance location */
270 	OUT_BATCH(0);	/* index buffer offset, ignored */
585 	OUT_BATCH(GEN5_3DSTATE_VERTEX_BUFFERS | 3);
586 	OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT | VB0_VERTEXDATA |
590 	OUT_BATCH(0);
591 	OUT_BATCH(~0); /* max address: disabled */
592 	OUT_BATCH(0);
604 	OUT_BATCH(GEN5_3DPRIMITIVE |
610 	OUT_BATCH(0);	/* vertex count, to be filled in later */
611 	OUT_BATCH(sna->render.vertex_index);
612 	OUT_BATCH(1);	/* single instance */
613 	OUT_BATCH(0);	/* start instance location */
614 	OUT_BATCH(0);	/* index buffer offset, ignored */
750 	OUT_BATCH(GEN5_URB_FENCE |
757 	OUT_BATCH(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
760 	OUT_BATCH(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
764 	OUT_BATCH(GEN5_CS_URB_STATE | 0);
765 	OUT_BATCH((URB_CS_ENTRY_SIZE - 1) << 4 | URB_CS_ENTRIES << 0);
772 	OUT_BATCH(GEN5_STATE_BASE_ADDRESS | 6);
773 	OUT_BATCH(kgem_add_reloc(&sna->kgem, /* general */
778 	OUT_BATCH(kgem_add_reloc(&sna->kgem, /* surface */
783 	OUT_BATCH(0); /* media */
784 	OUT_BATCH(kgem_add_reloc(&sna->kgem, /* instruction */
791 	OUT_BATCH(BASE_ADDRESS_MODIFY);
792 	OUT_BATCH(0);
793 	OUT_BATCH(BASE_ADDRESS_MODIFY);
809 		OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
811 	OUT_BATCH(GEN5_PIPELINE_SELECT | PIPELINE_SELECT_3D);
858 	OUT_BATCH(GEN5_3DSTATE_BINDING_TABLE_POINTERS | 4);
859 	OUT_BATCH(0);		/* vs */
860 	OUT_BATCH(0);		/* gs */
861 	OUT_BATCH(0);		/* clip */
862 	OUT_BATCH(0);		/* sf */
864 	OUT_BATCH(offset*4);
895 	OUT_BATCH(GEN5_3DSTATE_PIPELINED_POINTERS | 5);
896 	OUT_BATCH(sna->render_state.gen5.vs);
897 	OUT_BATCH(GEN5_GS_DISABLE); /* passthrough */
898 	OUT_BATCH(GEN5_CLIP_DISABLE); /* passthrough */
899 	OUT_BATCH(sna->render_state.gen5.sf[op->mask.bo != NULL]);
900 	OUT_BATCH(sna->render_state.gen5.wm + sp);
901 	OUT_BATCH(sna->render_state.gen5.cc + bp);
928 	OUT_BATCH(GEN5_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
929 	OUT_BATCH(0x00000000);
930 	OUT_BATCH(limit);
931 	OUT_BATCH(offset);
964 	OUT_BATCH(GEN5_3DSTATE_VERTEX_ELEMENTS |
967 	OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
970 	OUT_BATCH((VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) |
976 	OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
979 	OUT_BATCH(VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
1016 	OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
1018 	OUT_BATCH(dw);
1048 		OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
1050 		OUT_BATCH(dw);
1058 	OUT_BATCH(GEN5_PIPE_CONTROL |
1061 	OUT_BATCH(0);
1062 	OUT_BATCH(0);
1063 	OUT_BATCH(0);
1065 	OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
1093 		OUT_BATCH(MI_FLUSH);