Cross Reference: /xsrc/external/mit/xf86-video-intel/dist/src/sna/gen5

Lines Matching refs:gen5
245 	struct gen5_render_state *state = &sna->render_state.gen5;
581 	int id = op->u.gen5.ve_id;
599 	if (sna->kgem.nbatch == sna->render_state.gen5.last_primitive) {
617 	sna->render_state.gen5.last_primitive = sna->kgem.nbatch;
623 	int id = op->u.gen5.ve_id;
663 						     op->u.gen5.wm_kernel);
771 	assert(sna->render_state.gen5.general_bo->proxy == NULL);
775 				 sna->render_state.gen5.general_bo,
786 				 sna->render_state.gen5.general_bo,
815 	sna->render_state.gen5.needs_invariant = false;
831 	if (sna->render_state.gen5.needs_invariant)
839 	if (op->floats_per_vertex != sna->render_state.gen5.floats_per_vertex) {
841 		     sna->render_state.gen5.floats_per_vertex,
844 		sna->render_state.gen5.floats_per_vertex = op->floats_per_vertex;
852 	    sna->render_state.gen5.surface_table == offset)
855 	sna->render_state.gen5.surface_table = offset;
876 	     __FUNCTION__, op->u.gen5.ve_id & 2,
889 	     sna->render_state.gen5.last_pipelined_pointers & 0xffff,
890 	     (sna->render_state.gen5.last_pipelined_pointers >> 16) & 0x7fff,
891 	     sna->render_state.gen5.last_pipelined_pointers));
892 	if (key == sna->render_state.gen5.last_pipelined_pointers)
896 	OUT_BATCH(sna->render_state.gen5.vs);
899 	OUT_BATCH(sna->render_state.gen5.sf[op->mask.bo != NULL]);
900 	OUT_BATCH(sna->render_state.gen5.wm + sp);
901 	OUT_BATCH(sna->render_state.gen5.cc + bp);
903 	bp = (sna->render_state.gen5.last_pipelined_pointers & 0x7fff0000) != ((uint32_t)bp << 16);
904 	sna->render_state.gen5.last_pipelined_pointers = key;
921 	    sna->render_state.gen5.drawrect_limit == limit &&
922 	    sna->render_state.gen5.drawrect_offset == offset)
925 	sna->render_state.gen5.drawrect_offset = offset;
926 	sna->render_state.gen5.drawrect_limit = limit;
945 	struct gen5_render_state *render = &sna->render_state.gen5;
946 	int id = op->u.gen5.ve_id;
1082 	if (gen5_emit_pipelined_pointers(sna, op, op->op, op->u.gen5.wm_kernel)){
1126 		assert(op->u.gen5.ve_id >> 2);
1137 	    *(uint64_t *)(sna->kgem.batch + sna->render_state.gen5.surface_table) == *(uint64_t*)binding_table &&
1139 	     sna->kgem.batch[sna->render_state.gen5.surface_table+2] == binding_table[2])) {
1141 		offset = sna->render_state.gen5.surface_table;
1446 	tmp.u.gen5.wm_kernel = select_video_kernel(video, frame);
1447 	tmp.u.gen5.ve_id = 2;
2036 	tmp->u.gen5.wm_kernel =
2041 	tmp->u.gen5.ve_id = gen4_choose_composite_emitter(sna, tmp);
2283 	tmp->base.u.gen5.ve_id = gen4_choose_spans_emitter(sna, tmp);
2284 	tmp->base.u.gen5.wm_kernel = WM_KERNEL_OPACITY | !tmp->base.is_affine;
2340 	    *(uint64_t *)(sna->kgem.batch + sna->render_state.gen5.surface_table) == *(uint64_t*)binding_table) {
2342 		offset = sna->render_state.gen5.surface_table;
2471 	tmp.u.gen5.wm_kernel = WM_KERNEL;
2472 	tmp.u.gen5.ve_id = 2;
2640 	op->base.u.gen5.wm_kernel = WM_KERNEL;
2641 	op->base.u.gen5.ve_id = 2;
2690 	    *(uint64_t *)(sna->kgem.batch + sna->render_state.gen5.surface_table) == *(uint64_t*)binding_table) {
2693 		offset = sna->render_state.gen5.surface_table;
2804 	tmp.u.gen5.wm_kernel = WM_KERNEL;
2805 	tmp.u.gen5.ve_id = 1;
2978 	op->base.u.gen5.wm_kernel = WM_KERNEL;
2979 	op->base.u.gen5.ve_id = 1;
3073 	tmp.u.gen5.wm_kernel = WM_KERNEL;
3074 	tmp.u.gen5.ve_id = 1;
3124 		sna->render_state.gen5.drawrect_limit = -1;
3135 	sna->render_state.gen5.needs_invariant = true;
3136 	sna->render_state.gen5.ve_id = -1;
3137 	sna->render_state.gen5.last_primitive = -1;
3138 	sna->render_state.gen5.last_pipelined_pointers = 0;
3140 	sna->render_state.gen5.drawrect_offset = -1;
3141 	sna->render_state.gen5.drawrect_limit = -1;
3142 	sna->render_state.gen5.surface_table = -1;
3156 	kgem_bo_destroy(&sna->kgem, sna->render_state.gen5.general_bo);
3307 	struct gen5_render_state *state = &sna->render_state.gen5;
3415 	return "Ironlake (gen5)";