Lines Matching refs:clock
24 * For all supported programmable clock generators, the driver will ignore any
25 * XF86Config clock line and programme, as needed, the clock number reserved by
33 * best approximates the mode's clock frequency, where R is the crystal-
36 * Different clock generators have different restrictions on the value N, M and
39 * then encoded in a generator-specific way and used to programme the clock.
40 * The Mach64's clock divider is not used in this case.
57 * Definitions related to programmable clock generators.
121 * Recognise supported clock generators. This involves telling the
128 "%s programmable clock generator detected.\n",
132 "Reference clock %.3f MHz.\n",
136 "Reference clock %.6g/%d (%.3f) MHz.\n",
156 pScreenInfo->clock[0] = 25175;
157 pScreenInfo->clock[1] = 28322;
172 * This function is called to generate, if necessary, the data needed for clock
173 * programming, and set clock select bits in various register values.
195 "First two clocks of Chrontel 8398 clock generator are fixed\n");
200 /* Generate clock programme word, using units of kHz */
268 "Unable to programme clock %.3fMHz for mode %s.\n",
276 "\n Programming clock %d to %.3fMHz for mode %s."
286 /* Set clock select bits */
287 pATIHW->clock = ClockSelect;
300 * This function is called to programme a clock for the mode being set.
327 Programme = (SetBits(pATIHW->clock, ICS2595_CLOCK) |
351 out8(M64_DAC_MASK, (pATIHW->clock << 1) + 0x20U);
360 out8(M64_DAC_WRITE, pATIHW->clock);
375 tmp2 = pATIHW->clock << 1;
383 tmp &= ~(SetBits(1, PLL_VCLK0_XDIV) << pATIHW->clock);
384 tmp |= SetBits(D >> 2, PLL_VCLK0_XDIV) << pATIHW->clock;
388 tmp = PLL_VCLK0_FB_DIV + pATIHW->clock;
407 tmp2 = (pATIHW->clock << 2) + 0x40U;
424 tmp = (pATIHW->clock << 1) + 0x20U;