Lines Matching refs:x01
128 #define MGAOPM_DMA_BLIT (0x01 << 2)
133 #define MGAMAC_PW16 0x01
145 #define MGADWG_AUTOLINE_OPEN 0x01
167 #define MGADWG_RSTR ( 0x01 << 4 )
173 #define MGADWG_LINEAR ( 0x01 << 7 )
187 #define MGADWG_SOLID ( 0x01 << 11 )
191 #define MGADWG_ARZERO ( 0x01 << 12 )
193 #define MGADWG_SGNZERO ( 0x01 << 13 )
195 #define MGADWG_SHIFTZERO ( 0x01 << 14 )
203 #define MGADWG_BPLAN ( 0x01 << 25 )
215 #define MGADWG_PATTERN ( 0x01 << 29 )
216 #define MGADWG_TRANSC ( 0x01 << 30 )
243 #define MGA1064_OPT_SYS_CLK_PLL ( 0x01 << 0 )
247 #define MGA1064_OPT_SYS_CLK_DIS ( 0x01 << 2 )
248 #define MGA1064_OPT_G_CLK_DIV_1 ( 0x01 << 3 )
249 #define MGA1064_OPT_M_CLK_DIV_1 ( 0x01 << 4 )
251 #define MGA1064_OPT_SYS_PLL_PDN ( 0x01 << 5 )
252 #define MGA1064_OPT_VGA_ION ( 0x01 << 8 )
266 #define TVP3026_COL_PAL 0x01
280 #define TVP3026_SILICON_REV 0x01
318 #define MGA1064_COL_PAL 0x01
349 #define MGA1064_MUL_CTL_15bits 0x01
358 #define MGA1064_PIX_CLK_CTL_CLK_DIS ( 0x01 << 2 )
359 #define MGA1064_PIX_CLK_CTL_CLK_POW_DOWN ( 0x01 << 3 )
361 #define MGA1064_PIX_CLK_CTL_SEL_PLL ( 0x01 << 0 )
366 #define MGA1064_GEN_CTL_SYNC_ON_GREEN_DIS (0x01 << 5)
368 #define MGA1064_MISC_CTL_DAC_EN ( 0x01 << 0 )
369 #define MGA1064_MISC_CTL_VGA ( 0x01 << 1 )
372 #define MGA1064_MISC_CTL_VGA8 ( 0x01 << 3 )
373 #define MGA1064_MISC_CTL_DAC_RAM_CS ( 0x01 << 4 )
384 #define MGA1064_REMHEADCTL_CLKDIS ( 0x01 << 0 )
386 #define MGA1064_REMHEADCTL_CLKSL_PLL ( 0x01 << 1 )
442 #define MGA1064_DISP_CTL_DAC1OUTSEL_MASK 0x01
444 #define MGA1064_DISP_CTL_DAC1OUTSEL_EN 0x01
447 #define MGA1064_DISP_CTL_DAC2OUTSEL_CRTC1 (0x01 << 2)
452 #define MGA1064_DISP_CTL_PANOUTSEL_CRTC1 (0x01 << 5)
459 #define MGA1064_PWR_CTL_DAC2_EN (0x01 << 0)
460 #define MGA1064_PWR_CTL_VID_PLL_EN (0x01 << 1)
461 #define MGA1064_PWR_CTL_PANEL_EN (0x01 << 2)
462 #define MGA1064_PWR_CTL_RFIFO_EN (0x01 << 3)
463 #define MGA1064_PWR_CTL_CFIFO_EN (0x01 << 4)
479 #define MGAREG_C2CTL_C2_EN 0x01
485 #define MGAREG_C2CTL_PIXCLKSELH_MASK (0x01 << 14)
487 #define MGAREG_C2CTL_PIXCLKSEL_VDOCLK (0x01 << 1)
490 #define MGAREG_C2CTL_PIXCLKSEL_VDCLK (0x01 << 14)
492 #define MGAREG_C2CTL_PIXCLKSEL_CRISTAL (0x01 << 1) | (0x01 << 14)
493 #define MGAREG_C2CTL_PIXCLKSEL_SYSTEMPLL (0x02 << 1) | (0x01 << 14)
495 #define MGAREG_C2CTL_PIXCLKDIS_MASK (0x01 << 3)
496 #define MGAREG_C2CTL_PIXCLKDIS_DISABLE (0x01 << 3)
498 #define MGAREG_C2CTL_CRTCDACSEL_MASK (0x01 << 20)
500 #define MGAREG_C2CTL_CRTCDACSEL_CRTC2 (0x01 << 20)