Cross Reference: /xsrc/external/mit/xf86-video-nouveau/dist/src/nv50

Lines Matching refs:PUSH_DATA
93 	PUSH_DATA (push, dst->offset >> 32);
94 	PUSH_DATA (push, dst->offset);
96 	case 32: PUSH_DATA (push, NV50_SURFACE_FORMAT_BGRA8_UNORM); break;
97 	case 30: PUSH_DATA (push, NV50_SURFACE_FORMAT_RGB10_A2_UNORM); break;
98 	case 24: PUSH_DATA (push, NV50_SURFACE_FORMAT_BGRX8_UNORM); break;
99 	case 16: PUSH_DATA (push, NV50_SURFACE_FORMAT_B5G6R5_UNORM); break;
100 	case 15: PUSH_DATA (push, NV50_SURFACE_FORMAT_BGR5_X1_UNORM); break;
102 	PUSH_DATA (push, dst->config.nv50.tile_mode);
103 	PUSH_DATA (push, 0);
105 	PUSH_DATA (push, ppix->drawable.width);
106 	PUSH_DATA (push, ppix->drawable.height);
108 	PUSH_DATA (push, 1);
111 	PUSH_DATA (push, 0);
115 	PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
120 	PUSH_DATA (push, (src->offset + packed_y));
121 	PUSH_DATA (push, (src->offset + packed_y) >> 32 | mode);
122 	PUSH_DATA (push, 0x00300000);
123 	PUSH_DATA (push, width);
124 	PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
125 	PUSH_DATA (push, 0x03000000);
126 	PUSH_DATA (push, 0x00000000);
127 	PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
132 	PUSH_DATA (push, (src->offset + uv));
133 	PUSH_DATA (push, (src->offset + uv) >> 32 | mode);
134 	PUSH_DATA (push, 0x00300000);
135 	PUSH_DATA (push, width >> 1);
136 	PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | (height >> 1));
137 	PUSH_DATA (push, 0x03000000);
138 	PUSH_DATA (push, 0x00000000);
141 	PUSH_DATA (push, NV50TIC_0_0_MAPA_C1 | NV50TIC_0_0_TYPEA_UNORM |
147 	PUSH_DATA (push, NV50TIC_0_0_MAPA_C0 | NV50TIC_0_0_TYPEA_UNORM |
153 	PUSH_DATA (push, (src->offset + packed_y));
154 	PUSH_DATA (push, (src->offset + packed_y) >> 32 | mode);
155 	PUSH_DATA (push, 0x00300000);
156 	PUSH_DATA (push, width);
157 	PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
158 	PUSH_DATA (push, 0x03000000);
159 	PUSH_DATA (push, 0x00000000);
161 	PUSH_DATA (push, NV50TIC_0_0_MAPA_C2 | NV50TIC_0_0_TYPEA_UNORM |
167 	PUSH_DATA (push, NV50TIC_0_0_MAPA_C3 | NV50TIC_0_0_TYPEA_UNORM |
173 	PUSH_DATA (push, (src->offset + packed_y));
174 	PUSH_DATA (push, (src->offset + packed_y) >> 32 | mode);
175 	PUSH_DATA (push, 0x00300000);
176 	PUSH_DATA (push, (width >> 1));
177 	PUSH_DATA (push, (1 << NV50TIC_0_5_DEPTH_SHIFT) | height);
178 	PUSH_DATA (push, 0x03000000);
179 	PUSH_DATA (push, 0x00000000);
183 	PUSH_DATA (push, NV50TSC_1_0_WRAPS_CLAMP_TO_EDGE |
186 	PUSH_DATA (push, NV50TSC_1_1_MAGF_LINEAR |
189 	PUSH_DATA (push, 0x00000000);
190 	PUSH_DATA (push, 0x00000000);
191 	PUSH_DATA (push, 0x00000000);
192 	PUSH_DATA (push, 0x00000000);
193 	PUSH_DATA (push, 0x00000000);
194 	PUSH_DATA (push, 0x00000000);
195 	PUSH_DATA (push, NV50TSC_1_0_WRAPS_CLAMP_TO_EDGE |
198 	PUSH_DATA (push, NV50TSC_1_1_MAGF_LINEAR |
201 	PUSH_DATA (push, 0x00000000);
202 	PUSH_DATA (push, 0x00000000);
203 	PUSH_DATA (push, 0x00000000);
204 	PUSH_DATA (push, 0x00000000);
205 	PUSH_DATA (push, 0x00000000);
206 	PUSH_DATA (push, 0x00000000);
209 	PUSH_DATA (push, PFP_NV12);
212 	PUSH_DATA (push, 0);
215 	PUSH_DATA (push, 1);
217 	PUSH_DATA (push, 0x203);
262 		PUSH_DATA (push, sx2 << NV50_3D_SCISSOR_HORIZ_MAX__SHIFT | sx1);
263 		PUSH_DATA (push, sy2 << NV50_3D_SCISSOR_VERT_MAX__SHIFT | sy1 );
265 		PUSH_DATA (push, NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_TRIANGLES);
270 		PUSH_DATA (push, 0);