Cross Reference: /xsrc/external/mit/xf86-video-nsc/dist/src/gfx/disp

Lines Matching refs:READ_REG32
273       READ_REG32(DC_UNLOCK);
316 	    READ_REG32(DC_UNLOCK);
322 	 READ_REG32(DC_UNLOCK);
415    unlock = READ_REG32(DC_UNLOCK);
420    gcfg = READ_REG32(DC_GENERAL_CFG);
421    tcfg = READ_REG32(DC_TIMING_CFG);
458    lock = READ_REG32(DC_UNLOCK);
459    ocfg = READ_REG32(DC_OUTPUT_CFG) & ~(DC_OCFG_8BPP | DC_OCFG_555);
521    unlock = READ_REG32(DC_UNLOCK);
526    gcfg = READ_REG32(DC_GENERAL_CFG);
527    tcfg = READ_REG32(DC_TIMING_CFG);
632    vid_buffer_size = READ_REG32(DC_BUF_SIZE) & 0x3FFF0000;
751 	 tcfg = READ_REG32(DC_TIMING_CFG);
972    unlock = READ_REG32(DC_UNLOCK);
977    tcfg = READ_REG32(DC_TIMING_CFG);
978    timing1 = READ_REG32(DC_V_TIMING_1);
979    timing2 = READ_REG32(DC_V_TIMING_2);
1015    unsigned long lock = READ_REG32(DC_UNLOCK);
1017    value = READ_REG32(DC_LINE_DELTA) & 0xFFFFF000;
1059    lock = READ_REG32(DC_UNLOCK);
1171    unlock = READ_REG32(DC_UNLOCK);
1172    gcfg = READ_REG32(DC_GENERAL_CFG);
1286    unlock = READ_REG32(DC_UNLOCK);
1343    offset = READ_REG32(DC_FB_ST_OFFSET) & 0x003FFFFF;
1367    unlock = READ_REG32(DC_UNLOCK);
1368    gcfg = READ_REG32(DC_GENERAL_CFG);
1393    unlock = READ_REG32(DC_UNLOCK);
1394    gcfg = READ_REG32(DC_GENERAL_CFG);
1450    lock = READ_REG32(DC_UNLOCK);
1475    lock = READ_REG32(DC_UNLOCK);
1476    line_delta = READ_REG32(DC_LINE_DELTA) & 0xFF800FFF;
1511    lock = READ_REG32(DC_UNLOCK);
1512    buf_size = READ_REG32(DC_BUF_SIZE) & 0xFFFF01FF;
1536    lock = READ_REG32(DC_UNLOCK);
1537    gcfg = READ_REG32(DC_GENERAL_CFG);
1538    buf_size = READ_REG32(DC_BUF_SIZE);
1596    lock = READ_REG32(DC_UNLOCK);
1598    value = READ_REG32(DC_BUF_SIZE) & 0x0000FFFF;
1621    lock = READ_REG32(DC_UNLOCK);
1647    lock = READ_REG32(DC_UNLOCK);
1648    control = READ_REG32(MC_MEM_CNTRL1);
1671    if (READ_REG32(DC_TIMING_CFG) & DC_TCFG_TGEN)
1689    if (READ_REG32(DC_TIMING_CFG) & DC_TCFG_VNA)
1894       value = (READ_REG32(DC_LINE_DELTA) & 0x07FF) << 2;
1896       value = (READ_REG32(DC_LINE_DELTA) & 0x03FF) << 2;
1971    return ((READ_REG32(DC_BUF_SIZE) & 0x1FF) << 3);
2304    return ((unsigned short)((READ_REG32(DC_H_TIMING_1) & 0x07F8) + 8));
2319    return ((unsigned short)((READ_REG32(DC_H_TIMING_3) & 0x07F8) + 8));
2334    return ((unsigned short)(((READ_REG32(DC_H_TIMING_3) >> 16) & 0x07F8) +
2350    return ((unsigned short)(((READ_REG32(DC_H_TIMING_1) >> 16) & 0x07F8) +
2366    return ((unsigned short)((READ_REG32(DC_V_TIMING_1) & 0x07FF) + 1));
2381    return ((unsigned short)(((READ_REG32(DC_V_TIMING_3) >> 16) & 0x07FF) +
2397    return ((unsigned short)(((READ_REG32(DC_V_TIMING_1) >> 16) & 0x07FF) +
2415    switch (READ_REG32(DC_OUTPUT_CFG) & 3) {
2441       current_scan_line = (unsigned short)READ_REG32(DC_V_LINE_CNT) & 0x07FF;
2443 	  (unsigned short)(READ_REG32(DC_V_LINE_CNT) & 0x07FF));
2460    return (READ_REG32(DC_FB_ST_OFFSET) & 0x003FFFFF);
2475    return (READ_REG32(DC_CURS_ST_OFFSET) & 0x003FFFFF);
2496    return ((unsigned short)((READ_REG32(DC_H_TIMING_2) & 0x07F8) + 8));
2511    return ((unsigned short)(((READ_REG32(DC_H_TIMING_2) >> 16) & 0x07F8) +
2527    return ((unsigned short)((READ_REG32(DC_V_TIMING_2) & 0x07FF) + 1));
2542    return ((unsigned short)((READ_REG32(DC_V_TIMING_3) & 0x07FF) + 1));
2557    return ((unsigned short)(((READ_REG32(DC_V_TIMING_2) >> 16) & 0x07FF) +
2579    data = READ_REG32(DC_PAL_DATA);
2604       data = READ_REG32(DC_PAL_DATA);
2623    return (READ_REG32(DC_GENERAL_CFG) & DC_GCFG_CURE);
2638    return ((READ_REG32(DC_CURSOR_X) & 0x07FF) |
2639 	   ((READ_REG32(DC_CURSOR_Y) << 16) & 0x03FF0000));
2654    return (((READ_REG32(DC_CURSOR_X) >> 11) & 0x01F) |
2655 	   ((READ_REG32(DC_CURSOR_Y) << 5) & 0x1F0000));
2677    data = READ_REG32(DC_PAL_DATA);
2697    gcfg = READ_REG32(DC_GENERAL_CFG);
2718    offset = READ_REG32(DC_CB_ST_OFFSET) & 0x003FFFFF;
2736    pitch = (unsigned short)(READ_REG32(DC_LINE_DELTA) >> 12) & 0x07FF;
2754    size = (unsigned short)((READ_REG32(DC_BUF_SIZE) >> 9) & 0x7F) - 1;
2773    valid = (int)READ_REG32(MC_DR_ACC) & 1;
2792    return (READ_REG32(DC_VID_ST_OFFSET) & 0x003FFFFF);
2812    return ((READ_REG32(DC_BUF_SIZE) >> 10) & 0x000FFFC0);
2827    if (READ_REG32(MC_MEM_CNTRL1) & MC_XBUSARB)